Parity generator with serial input and parallel output vhdl code

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity parity_gen is
 
  port (
    clk       : in  std_logic;
    rst_a     : in  std_logic;
    valid_in  : in  std_logic;
    d_in      : in  std_logic;          -- input serial data stream
    valid_out : out std_logic;
    parity    : out std_logic;
    data_o    : out std_logic_vector (7 downto 0));

end parity_gen;

architecture parity_gen_arch of parity_gen is

  component d_ff is
 
  port (
     rst  : in  std_logic;               -- asynchronous reset
     clk  : in  std_logic;               -- clock
     en   : in  std_logic;               -- control signal 
     d_in : in  std_logic;               -- input data
     q    : out std_logic                -- output data
    );           

  end component;
 
  function parity_gen_func (par : in std_logic_vector (7 downto 0)) return std_logic is
  begin
  return par(0)xor par(1)xor par(2)xor par(3)xor par(4)xor par(5)xor par(6)xor par(7);
  end parity_gen_func;

  signal count : std_logic_vector (2 downto 0) := "000";
  signal temp : std_logic_vector (7 downto 0);

begin  -- parity_gen_arch

   d_ff1: d_ff port map (rst_a, clk, valid_in, d_in, temp(0));
   d_ff2: d_ff port map (rst_a, clk, valid_in, temp(0), temp(1));
   d_ff3: d_ff port map (rst_a, clk, valid_in, temp(1), temp(2));
   d_ff4: d_ff port map (rst_a, clk, valid_in, temp(2), temp(3));
   d_ff5: d_ff port map (rst_a, clk, valid_in, temp(3), temp(4));
   d_ff6: d_ff port map (rst_a, clk, valid_in, temp(4), temp(5));
   d_ff7: d_ff port map (rst_a, clk, valid_in, temp(5), temp(6));
   d_ff8: d_ff port map (rst_a, clk, valid_in, temp(6), temp(7));
  
data_o<= temp;
parity <= parity_gen_func(temp);
  
p1:   process (clk, rst_a)
        begin       
    if rst_a = '1' then                 -- asynchronous reset
      valid_out <= '0';
     
    elsif clk'event and clk ='1' then
    if valid_in = '1' then
        count<= count + '1';   
    end if; 
    if count = "111" then
        valid_out <= '1';
    else
        valid_out <= '0';
    end if;
    end if;
  end process p1;
 
end parity_gen_arch;