Vhdl code for barrel shifter with single cycle

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity barrel_shifter is
 
  port (
    d_in        : in  bit_vector(7 downto 0);   -- input vector
    d_out       : out bit_vector(7 downto 0);   -- shifted output
    shift_lt_rt : in  bit;                      -- 0=>left_operation 1=>right_operation
    shift_by    : in  bit_vector(2 downto 0);   -- 000=> parallel load other=>shift amount
    clk         : in  bit;                      -- clock signal
    rst_a       : in  bit);                     -- reset signal

end barrel_shifter;

architecture beh of barrel_shifter is

begin  -- beh
 p1: process (clk,rst_a,shift_by,shift_lt_rt)
variable x,y : bit_vector(7 downto 0);
variable ctrl0,ctrl1,ctrl2 : bit_vector(1 downto 0);
 begin  -- process p1
ctrl0:=shift_by(0) & shift_lt_rt;
ctrl1:=shift_by(1) & shift_lt_rt;
ctrl2:=shift_by(2) & shift_lt_rt;
if(rst_a = '1') then
d_out<="00000000";
elsif(clk'event and clk = '1') then

if (shift_by="000")then
  assert(false) report "Parallel load" severity warning;
elsif(shift_lt_rt='1')then
  assert(false) report "right shift" severity warning;
elsif(shift_lt_rt='0')then
  assert(false) report "left shift" severity warning;
 end if;

case ctrl0 is
  when "00"|"01" =>x:=d_in ;
  when "10" =>x:=d_in(6 downto 0) & d_in(7);
  when "11" =>x:=d_in(0) & d_in(7 downto 1);
  when others => null;
end case;
case ctrl1 is
  when "00"|"01" =>y:=x;
  when "10" =>y:=x(5 downto 0) & x(7 downto 6);
  when "11" =>y:=x(1 downto 0) & x(7 downto 2);
  when others => null;
end case;
case ctrl2 is
  when "00"|"01" =>d_out<=y ;
  when "10"|"11" =>d_out<= y(3 downto 0) & y(7 downto 4);
  when others => null;
end case;
end if;
  end process p1;
end beh;