Universal shifter in verilog with test bench

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// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module uni_shift_8b(op,clk,rst_a, load,sh_ro_lt_rt,ip);
  output reg [7:0] op;
  input load;
  input [1:0] sh_ro_lt_rt;
  input [7:0] ip;
  input clk, rst_a;
 
  reg [7:0]temp;
 
 
 
  always @(posedge clk or posedge rst_a)
   begin
     if (rst_a)
      
       op = 0;
     
     else   
       case(load)
         1'b1:
          begin                            //Load Input
            temp = ip;
          //  op = temp;
          end
         1'b0:                             //Operation
          case (sh_ro_lt_rt)
            2'b00:  op = temp<<1;     //Left Shift
            2'b01:  op = temp>>1;     //Right Shift
            2'b10:  op = {temp[6:0],temp[7]}; //Rotate Left
            2'b11:  op = {temp[0], temp[7:1]};  //Rotate Right
                  
            default: $display("Invalid Shift Control Input");
          endcase
     
       
        
        default: $display("Invalid Load Control Input");
        endcase
  
    end
   
  endmodule
         
   -----------------------------------------------------------

test bench
----------------------------------------------------------------
`timescale 1ns/1ps

module uni_shift_8b_tst;
  reg [7:0] ip;
  reg [1:0] sh_ro_lt_rt;
  reg         load,rst_a,clk;
  wire [7:0] op;


   uni_shift_8b u1 (.op(op), .ip(ip), .sh_ro_lt_rt(sh_ro_lt_rt), .load(load) , .rst_a(rst_a) , .clk(clk));

initial
  begin
     clk=1'b1;
     forever #50 clk=~clk;  
  end
 
   initial
     begin
    ip = 8'b11001100;
    rst_a = 1'b1;
    load = 1'b1;
    sh_ro_lt_rt = 2'b00;
    #100;
   
    ip = 8'b10001100;
    rst_a = 1'b0;
    load = 1'b1;
    sh_ro_lt_rt = 2'b01;
    #100;
   
    ip = 8'b11001100;

    load = 1'b0;
    sh_ro_lt_rt = 2'b01;
    #100;
   
    ip = 8'b10101101;
   
    load = 1'b1;
    sh_ro_lt_rt = 2'b01;
    #100;
   
    ip = 8'b11001101;

    load = 1'b0;
    sh_ro_lt_rt = 2'b01;
    #100;

    ip = 8'b11101100;
    load = 1'b1;
    sh_ro_lt_rt = 2'b10;
    #100;

    ip = 8'b11110000;
    load = 1'b0;
    sh_ro_lt_rt = 2'b10;
    #100;

    ip = 8'b11001100;
    load = 1'b1;
    sh_ro_lt_rt = 2'b11;
    #100;

    ip = 8'b11001101;
    load = 1'b0;
    sh_ro_lt_rt = 2'b11;
    #100;
   
    ip = 8'b11001000;
    load = 1'b1;
    sh_ro_lt_rt = 2'b11;
    #100;
    $stop;
     end // initial begin
   endmodule