Sequential multiplier using booth algorithm in verilog with test bench

//-----------------------------------------------------
// Design Name : Design and verify a sequential multiplier using Booths algorithm
// File Name   : booth_seq_multi.v
// Function    : Signed multiplication
// Author      :  Sidharth(DVLSI 31)
//-----------------------------------------------------
module booth_seq_multi(op,clk,rst_a,load,a,b);

   //parameter declaration-----------------------------
   parameter ip1_data_width = 4;
   parameter ip2_data_width = 4;
   parameter op_data_width  = ip1_data_width + ip2_data_width;
   parameter reg_data_width =ip1_data_width + ip2_data_width + 1;
  
   integer i;
  

   //input output declaration--------------------------
   output reg [op_data_width-1:0] op;
   input                   clk,rst_a,load;
   input [ip1_data_width-1:0]       a;
   input [ip2_data_width-1:0]       b;
  
   //register declaration------------------------------
   reg [reg_data_width-1:0]     tmp_a,tmp_s,tmp_p;
   reg [ip1_data_width-1:0]     tmp_abar,tmp_a2s,tmp_a1,tmp_b;
  
   
  always @(posedge clk)
    begin
       if(load)                  // Register the inputs
     begin
        tmp_a1=a;
        tmp_b=b;
     end
    end
  
   always @ (posedge clk,posedge rst_a)
   begin
    if(rst_a)
      op=0;
    else
      begin
       if(~load)
         begin
        tmp_abar= ~ tmp_a1;
        tmp_a2s = (tmp_abar + 1);   
        tmp_a={tmp_a1,5'b00000};
        tmp_s={tmp_a2s,5'b00000};
        tmp_p={4'b0000,tmp_b,1'b0};
       
        for(i=0;i<4;i=i+1)
          begin
             case(tmp_p[1:0])

               2'b00 : tmp_p = {tmp_p[8],tmp_p[8:1]};
               2'b01 :begin tmp_p =tmp_p + tmp_a;
                            tmp_p = {tmp_p[8],tmp_p[8:1]};
                      end
               2'b10 :begin tmp_p = tmp_p + tmp_s;
                            tmp_p = {tmp_p[8],tmp_p[8:1]};
                          end
               2'b11 : tmp_p = {tmp_p[8],tmp_p[8:1]};
               default: tmp_p = 9'bx;
             endcase // case (tmp_p[1:0])
          end // for (i=0;i<4;i=i+1)

              op=tmp_p[8:1];
         end // if (~load)
       end // else: !if(rst_a)
     end
endmodule // booth_seq_multi

----------------------------------------------------------------

test bench
----------------------------------------------------------------
`timescale 1ns/1ps
module booth_seq_multi_tb;
reg [3:0] a,b;
reg load,clk,rst_a;
wire [7:0] op;


booth_seq_multi u1 (.op(op), .a(a), .b(b), .load(load), .clk(clk), .rst_a(rst_a));

initial
begin
clk=1'b1;
forever #50 clk=~clk;
end

initial
begin
rst_a=1'b1;
a=4'b1010;
b=4'b0010;
load=1'b1;

#100;
rst_a=1'b0;
a=4'b1110;
b=4'b0101;
load=1'b1;

#100;
a=4'b1000;
b=4'b0101;
load=1'b0;
rst_a=1'b0;
#100;
a=4'b1010;
b=4'b1111;
load=1'b1;
rst_a=1'b0;
#100;
a=4'b1111;
b=4'b1001;
load=1'b1;
rst_a=1'b0;

#100;
a=4'b1011;
b=4'b0100;
load=1'b0;
rst_a=1'b0;
#100;

a=4'b1010;
b=4'b1000;
load=1'b1;
rst_a=1'b0;
#100;

a=4'b1000;
b=4'b0101;
load=1'b0;
rst_a=1'b0;
#100;


$stop;
end
endmodule