sequential multiplier in verilog

/////////////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module seq_multi_4b(op,ready_out,a,b,load,clk,rst_a);
output reg [7:0] op;
output reg ready_out;
input [3:0] a,b;
input load,clk,rst_a;
reg [7:0] tmp,tmp0,tmp1,tmp2,tmp3;
reg [3:0] tmp_a;
  
always @(posedge clk)
  begin
     if(load)
       tmp_a=a;
       tmp={4'b0000,b};
  end
  
  

always @(tmp_a,load,tmp)
//begin
//if(load)
begin
case (tmp_a[0])
        1'b0:tmp0=8'b0000_0000;
        1'b1:tmp0=tmp;
endcase
case (tmp_a[1])
        1'b0:tmp1=8'b0000_0000;
        1'b1:tmp1=tmp<<1;
endcase
case (tmp_a[2])
        1'b0:tmp2=8'b0000_0000;
        1'b1:tmp2=tmp<<2;
endcase
case (tmp_a[3])
        1'b0:tmp3=8'b0000_0000;
        1'b1:tmp3=tmp<<3;
endcase // case (tmp_a[3])
//end
end // always @ (tmp,tmp_a)


always @ (posedge clk,posedge rst_a)
begin
     if(rst_a)
       begin
      op=0;
      ready_out=0;
    end
     else
       if(load)
         begin
        op=tmp0+tmp1+tmp2+tmp3;
        ready_out=1'b1;
        end
end

endmodule