Single Port RAM in VHDL using generate statement

//////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;

entity memory_sp is
 
  port (
    clk      : in  std_logic;
    address  : in  std_logic_vector(3 downto 0);   -- input address
    rd_wr    : in  std_logic;           -- read write signal  1=read 0=write
    cs       : in  std_logic;           -- chip select
    data : inout std_logic_vector(8 downto 0));  -- output data

end memory_sp;


architecture beh of memory_sp is

  type dataout is array (15 downto 0,8 downto 0) of std_logic;
  signal d1 : dataout;
  signal cs_r : std_logic_vector(15 downto 0);  -- chip enable signal
  signal addr_out : std_logic_vector(15 downto 0);  -- address from the decoder
  component dff_async_reset
      port (
          data    :in  std_logic;  -- Data input
          clk     :in  std_logic;  -- Clock input
          enb     :in  std_logic;   -- enable pin
          q       :out std_logic  -- Q output
            );
  end component;

  component deco4x16
 
  port (
    ip : in  std_logic_vector(3 downto 0);   -- input
    op : out std_logic_vector(15 downto 0));  -- output

    end component;
 
begin  -- beh
 
  addr: deco4x16 port map (address,addr_out);
  process(address,cs,rd_wr)
    begin
      cs_gen: for k in 0 to 15 loop
       
  
 end loop cs_gen;
 
 
row1: for i in 0 to 15 generate
  col: for j in 0 to 8 generate
  if (j>=0 and j<8) generate
  row1: dff_async_reset port map (data_in(i),clk,cs_r(i),d1(i,j));
  end generate;

  if (j=8) generate
  par1: dff_async_reset port map (parity_in,clk,cs_r(i),d1(i,j));
  end generate;

  end generate col;
 
end generate dff;

end beh;