System Verilog Inheritance example

/*-----------------------------------BASE CLASS----------------*/

class base;
   logic [7:0] data;

   task increament(logic[7:0] temp);
     data=temp+1;
   endtask // increament

   task random();
      this.data=$random;
   endtask // random

endclass // base

/*-----------------------------------DERIVED CLASS----------------*/
class derived extends base;
   logic[7:0] packet[];
   int size;

   function new(int size);
      this.size=size;
      packet=new[size];
   endfunction // new

endclass // derived

/*-----------------------------------MODULE----------------*/

module top;

   logic[7:0] din=8'b0;
   logic[7:0] dout[];

   reg      clk=0;
   reg      reset=0;
   reg      en=0;
   int      count=0;

   initial
     begin
dout=new[pkt1.size];
     end

   always #50 clk = ~clk;

   always@(posedge clk)
     begin
if(count<pkt1.size)
 begin
    en=1;
    pkt1.increament(din);
    pkt1.packet[count]=pkt1.data;
    count+=1;
    din=din+1;
 end
else
 begin
    en=0;
    dout=pkt1.packet;
 end // else: !if(count<pkt1.size)
     end // always@ (posedge clk)

   derived pkt1 = new(5);

   endmodule