Finite state machine -pattern checker in vhdl

When a certain serial binary communication
channel is operating correctly, all blocks of 0's are
of even length and all blocks of 1's are of odd
length. The machine should produce and output
pulse z = 1 whenever discrepancy from the above
pattern is detected.
Example:
X : 0 0 1 0 0 0 1 1 1 0 1 1 0 0…
Z : 0 0 0 0 0 0 1 0 0 0 1 0 1 0…



library ieee;
use ieee.std_logic_1164.all;

entity fsm_prob3 is
 
  port (
    clk                : in  std_logic;
    rst_a              : in  std_logic;
    ip                 : in  std_logic;
    op                 : out std_logic);

end fsm_prob3;

architecture fsm_arch of fsm_prob3 is

  type state_t is (s_idle,s1 ,s2, s3);
  signal present_state : state_t;
  signal next_state : state_t;
 
begin  -- fsm_arch

p1: process (present_state,ip)
begin  -- process p1

  case present_state is

  when s_idle =>
    if ip='1' then
      op <= '0';
      next_state <= s1;
      else
        op <= '0';
        next_state <= s2;
    end if;

  when s1 =>
    if ip = '1' then
      op <= '0';
      next_state <= s3;
      else
        op<='0';
        next_state <= s2;
    end if;

  when s2 =>
    if ip = '1' then
      op <= '1';
      next_state <= s1;
      else
        op <= '0';
        next_state <= s_idle;
    end if;

  when s3 =>
    if ip = '1' then
      op <= '0';
      next_state <= s1;
      else
        op <= '1';
        next_state <= s2;
    end if; 
  end case;
end process p1;

seq_p: process (clk, rst_a)
begin  -- process seq_p
  if rst_a = '1' then                   -- asynchronous reset (active high)
   
    present_state <= s_idle;
  elsif clk'event and clk = '1' then    -- rising clock edge
   
    present_state <= next_state;
  end if;
end process seq_p;
 

end fsm_arch;