Barrel shifter with multi cycle vhdl code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity barrel_shifter_multi is
 
  port (
    d_in        : in  bit_vector(7 downto 0);   -- input vector
    d_out       : out bit_vector(7 downto 0);   -- shifted output
    shift_lt_rt : in  bit;                      -- 0=>left_operation 1=>right_operation
    shift_by    : in  bit_vector(2 downto 0);   -- 000=> parallel load other=>shift amount
    clk         : in  bit;                      -- clock signal
    rst_a       : in  bit);                     -- reset signal

end barrel_shifter_multi;

architecture beh of barrel_shifter_multi is
signal x,y,z : bit_vector(7 downto 0);
signal tmp,tmp2,tmp3 : bit_vector(7 downto 0);
signal ctrl0,ctrl1,ctrl2 : bit_vector(1 downto 0);
begin  -- beh

--ctrl0<=shift_by(0) & shift_lt_rt;
--ctrl1<=shift_by(1) & shift_lt_rt;
--ctrl2<=shift_by(2) & shift_lt_rt;

p1: process (clk, rst_a)
begin  -- process p1
  if rst_a = '1' then                   -- asynchronous reset (active high)
    tmp<="00000000";
  elsif clk'event and clk = '1' then    -- rising clock edge
    tmp<=d_in;
    ctrl0<=shift_by(0) & shift_lt_rt;
  end if;
end process p1;


s1: process (ctrl0,tmp,clk)
begin  -- process p2
case ctrl0 is
  when "00"|"01" =>x<=tmp ;
  when "10" =>x<=tmp(6 downto 0) & tmp(7);
  when "11" =>x<=tmp(0) & tmp(7 downto 1);
  when others => null;
end case;
end process s1;

p2: process (clk, rst_a)
begin  -- process p1
  if rst_a = '1' then                   -- asynchronous reset (active high)
    tmp2<="00000000";
  elsif clk'event and clk = '1' then    -- rising clock edge
    tmp2<=x;
    ctrl1<=shift_by(1) & shift_lt_rt;
  end if;
end process p2;

s2: process (ctrl1,tmp2,clk)
begin  -- process s2
  case ctrl1 is
  when "00"|"01" =>y<=tmp2;
  when "10" =>y<=tmp2(5 downto 0) & tmp2(7 downto 6);
  when "11" =>y<=tmp2(1 downto 0) & tmp2(7 downto 2);
  when others => null;
end case;
end process s2;

p3: process (clk, rst_a)
begin  -- process p1
  if rst_a = '1' then                   -- asynchronous reset (active high)
    tmp3<="00000000";
  elsif clk'event and clk = '1' then    -- rising clock edge
    tmp3<=y;
    ctrl2<=shift_by(2) & shift_lt_rt;
  end if;
end process p3;

s4: process (ctrl2,tmp3,clk)
begin  -- process s4
  case ctrl2 is
  when "00"|"01" =>z<=tmp3 ;
  when "10"|"11" =>z<= tmp3(3 downto 0) & tmp3(7 downto 4);
  when others => null;
end case;

end process s4;

p4: process (clk, rst_a)
begin  -- process p1
  if rst_a = '1' then                   -- asynchronous reset (active high)
    d_out<="00000000";
  elsif clk'event and clk = '1' then    -- rising clock edge
    d_out<=z;
  end if;
end process p4;
end beh;