User defined package in vhdl example

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

package combo_logic is

  function mux2x1 (d1,d2,sel : std_logic) return std_logic;
  function parity_chk (signal d_in : std_logic_vector) return std_logic;
  function left_shift (signal d_in : std_logic_vector; signal shift_by : integer)  return bit_vector;
  function right_shift (signal d_in : std_logic_vector; signal shift_by : integer) return bit_vector; 
 
end combo_logic;


package body combo_logic is
--------------------------------------------------------------------------------
--function body for mux2x1
-------------------------------------------------------------------------------
 function mux2x1 (d1,d2,sel : std_logic) return std_logic
   is begin

        if(sel='0')then

        return d1;

        else

        return d2;
     end if;
 end mux2x1;
 ------------------------------------------------------------------------------
 --function body for parity_chk
 ------------------------------------------------------------------------------

 function parity_chk (signal d_in : std_logic_vector) return std_logic
   is
   constant len : integer:=(d_in)'length-1;
   variable tmp : std_logic:='0';
 begin
   for i in len loop
     tmp:=tmp xor d_in(i);
   end loop;  -- i
  
 return tmp;
 end function;
-------------------------------------------------------------------------------
--function body for left_shift
-------------------------------------------------------------------------------

 function left_shift (signal d_in : std_logic_vector; signal shift_by : integer)  return bit_vector
   is
   constant len : integer:=d_in'length;
   variable tmp : bit_vector(len-1 downto 0):=to_bitvector(d_in);
  
 begin
  assert len>shift_by report "shift_by greater than length of input data" severity error;
  tmp:=tmp rol shift_by;
  return tmp;
 end function;
-------------------------------------------------------------------------------
--function body for right_shift
-------------------------------------------------------------------------------

 function right_shift (signal d_in : std_logic_vector; signal shift_by : integer)  return bit_vector
   is
   constant len : integer:=d_in'length;
   variable tmp : bit_vector(len-1 downto 0):=to_bitvector(d_in);
 begin
   assert len>shift_by report "shift_by greater than length of input data" severity error;
  tmp:=tmp ror shift_by;
  return tmp;
 end function;

end combo_logic;