synchronous up down counter vhdl code and test bench

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity up_down_counter is
 
  port(clk, rst_a, mode : in std_logic;  --mode=1 up counting, mode=0 down counting
        q : out std_logic_vector(3 downto 0));

end up_down_counter;

architecture archi of up_down_counter is
  signal tmp: std_logic_vector(3 downto 0);
  begin 
    process (clk, rst_a)
      begin
        if (rst_a='1') then
          tmp <= "0000";
        elsif (clk'event and clk='1') then
          if (mode='1') then
            tmp <= tmp + 1;
          else
            tmp <= tmp - 1;
          end if;
        end if;
    end process;
    q <= tmp;
end archi;


Test Bench

 library ieee;
use ieee.std_logic_1164.all;

entity up_down_counter_tst is
 
end up_down_counter_tst;

architecture beh of up_down_counter_tst is
component up_down_counter
  port(clk, rst_a,mode : in std_logic;
      q : out std_logic_vector(3 downto 0));
end component;
signal clk_s,rst_a_s,mode_s : std_logic;
signal q_s : std_logic_vector(3 downto 0);
begin  -- beh

  u1 : up_down_counter port map (
    clk   => clk_s,
    rst_a => rst_a_s,
    mode  => mode_s,
    q     => q_s);

  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 55 ns;
    clk_s <= '0';
    wait for 55 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '0';
   wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;
  end process tst;
  end beh;