4 bit adder/substractor using full adder

library ieee;
use ieee.std_logic_1164.all;

entity add_sub_4b_using_fa is
 
  port (
    a, b : in  std_logic_vector(3 downto 0);   -- input bits
    enb  : in  std_logic;               -- en=0=>addition  ,  en=1 =>subtract
    c    : inout std_logic_vector(3 downto 0);   -- carry
    sd    : out std_logic_vector(3 downto 0));  -- sum/diff

end add_sub_4b_using_fa;

architecture beh of add_sub_4b_using_fa is
component full_adder
    port (
    ip1 : in  std_logic;
    ip2 : in  std_logic;
    ip3 : in  std_logic;
    sum : out std_logic;
    ca  : out std_logic);
end component;

component my_xor
  port (
    ip1 : in  std_logic;
    ip2 : in  std_logic;
    op1 : out std_logic);
end component;

signal b_s: std_logic_vector(3 downto 0);

begin  -- beh

u1: my_xor port map (enb,b(0),b_s(0));
u2: my_xor port map (enb,b(1),b_s(1));
u3: my_xor port map (enb,b(2),b_s(2));
u4: my_xor port map (enb,b(3),b_s(3));
u5: full_adder port map (a(0),b_s(0),enb,sd(0),c(0));
u6: full_adder port map (a(1),b_s(1),c(0),sd(1),c(1));
u7: full_adder port map (a(2),b_s(2),c(1),sd(2),c(2));
u8: full_adder port map (a(3),b_s(3),c(2),sd(3),c(3));
 

end beh;