d flipflop with setup/hold violation, reset recovery, clock width violation and output transition vhdl code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

 
  entity d_flipflop is
   
    generic (
          constant t_setup       : time := 5 ns;      -- setup time
          constant t_hold        : time := 5 ns;      -- hold time
          constant clk_width     : time := 54 ns;     -- clock width
          constant trans_time    : time := 3 ns;      -- output transition delay
          constant rst_reco_time : time := 3 ns       -- reset recovery time
    );
      port (
          data    :in  std_logic;  -- Data input
          clk     :in  std_logic;  -- Clock input
          reset_a :in  std_logic;  -- Reset input
          q       :out std_logic;  -- Q output
          load    :in  std_logic   -- load the input
      );
  end entity;
 
  architecture beh of d_flipflop is

    signal tmp : std_logic;
   
  begin

    p1:  process (clk,reset_a,load)
           begin
          
          if (reset_a = '1') then
              tmp <= '0' after 3 ns;
          elsif(rising_edge(clk)) then
              if(load = '1') then
              tmp <= '1'after 3 ns;
              else
                tmp<= data after 3 ns;
                end if;           
          end if;
        
       end process p1;

       chk_st: process (clk)
          begin  -- process chk_st
            if(clk'event and clk='1')then
              assert (data'stable(t_setup)) report "setup violation" severity error;
            end if;
          end process chk_st;

       chk_ht: process (clk'delayed(t_hold))
          begin  -- process chk_ht
            if(clk'delayed(t_hold)'event and clk'delayed(t_hold) = '1') then
              assert (data'last_event >= t_hold) report "hold time violation" severity error;
            end if;
          end process chk_ht;
         

       chk_wd: process (clk)
          variable last_time : time := 0 ns;
          begin  -- process chk_st
            assert (now-last_time > clk_width)
              report "clock width violation"
              severity warning;
            last_time := now;        
       end process chk_wd;
      
      
      chk_rst: process (clk,reset_a)
      begin  -- process chk_rst
        if(clk'event and clk='1')then
          assert (reset_a'stable(rst_reco_time)) report "reset recovery violation" severity warning;
        end if;
      end process chk_rst;
         
       chk: process
       begin  -- process chk
              if(clk'event and clk='1')then
                 wait for trans_time;
                  if(tmp'event and tmp='0') then
                    assert (not(clk'last_event-tmp'last_event=trans_time))
                    report "output dealy for high to low transition violation"
                    severity warning;
                 elsif(tmp'event and tmp='1') then
                    assert (not(clk'last_event-tmp'last_event=trans_time))
                    report "output dealy for low to high transition violation"
                    severity warning;
                  end if;
                end if;
                wait on clk,tmp;
              end process chk;
       q<=tmp;    

end architecture;

Test bench
--------------------------

library ieee;
use ieee.std_logic_1164.all;

entity d_flipflop_tst is
 
end d_flipflop_tst;

architecture beh of d_flipflop_tst is
component d_flipflop
  port (
    data, load, reset_a, clk: in  std_logic;   -- inputs
    q                             : out std_logic);  -- output
end component;
  signal data_s,load_s,reset_a_s,clk_s : std_logic := '0';
  signal q_s : std_logic;
begin  -- beh

  u1 : d_flipflop port map (
    data    => data_s,
    load    => load_s,
    reset_a => reset_a_s,
    clk     => clk_s,
    q       => q_s);

  tst_p: process
  begin  -- process tst_p
    clk_s <= '1';
    wait for 55 ns;
    clk_s <= '0';
    wait for 55 ns;
  end process tst_p;

 dff: process
 begin  -- process dff
   reset_a_s <= '1';
   load_s <= '1';
   data_s <= '0';
   wait for 109 ns;
   reset_a_s <= '0';
   load_s <= '1';
   data_s <= '1';
   wait for 112 ns;
   reset_a_s <= '0';
   load_s <= '0';
   data_s <= '0';
   wait for 100 ns;
   reset_a_s <= '0';
   load_s <= '0';
   data_s <= '1';
   wait for 100 ns;
  
 end process dff;
end beh;