up counter with preload vhdl code and test bench

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity up_counter_sync_preload is
 
  port(clk, rst_a,load : in std_logic;
       ip: in std_logic_vector(3 downto 0);
        q : out std_logic_vector(3 downto 0));

end up_counter_sync_preload;

architecture archi of up_counter_sync_preload is
  signal tmp: std_logic_vector(3 downto 0);
  begin 
    process (clk, rst_a)
      begin
        if (rst_a='1') then
          tmp <= "0000";
       elsif (clk'event and clk='1') then
          if (load='1') then
            tmp <= ip;
           
            assert (not(tmp - tmp'last_value = "0001"))
            report "counter difer by 1"
            severity warning;
         
          else
          tmp <= tmp + '1';
          end if;

      end if;

    end process;
    q <= tmp;

end archi;

--------------------------------
Test Bench
--------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity up_counter_sync_preload_tst is
 
end up_counter_sync_preload_tst;

architecture beh of up_counter_sync_preload_tst is
component up_counter_sync_preload
  port(clk, rst_a,load : in std_logic;
       ip: in std_logic_vector(3 downto 0);
        q : out std_logic_vector(3 downto 0));
end component;
signal clk_s,rst_a_s,load_s : std_logic;
signal ip_s,q_s : std_logic_vector(3 downto 0);
begin  -- beh

  u1 : up_counter_sync_preload port map (
    clk   => clk_s,
    rst_a => rst_a_s,
    load  => load_s,
    ip    => ip_s,
    q     => q_s);

  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 55 ns;
    clk_s <= '0';
    wait for 55 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;
    rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
        rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
        rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
        rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
        rst_a_s <= '0';
    load_s <= '1';
    ip_s <= "0101";
    wait for 100 ns;
        rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
  end process tst;
  end beh;