d flipflop with asynchronous reset enable and load vhdl code and test bench

library ieee;
use ieee.std_logic_1164.all;
 
  entity dff_async_reset is
      port (
          data    :in  std_logic;  -- Data input
          clk     :in  std_logic;  -- Clock input
          reset_a :in  std_logic;  -- Reset input
          q       :out std_logic;  -- Q output
          enb     :in  std_logic;  -- enable pin
          load    :in  std_logic   -- load the input
      );
  end entity;
 
  architecture beh of dff_async_reset is
 
  begin
      process (clk,reset_a,enb,load)
           begin
          
          if (reset_a = '1') then
              q <= '0';
          elsif(rising_edge(clk) and enb ='1') then
              if(load = '1') then
              q <= '1';
              else
                q<= data;
                end if;           
          end if;
    end process;
end architecture;



test bench
---------------------

library ieee;
use ieee.std_logic_1164.all;

entity dff_async_reset_tst is
 
end dff_async_reset_tst;

architecture beh of dff_async_reset_tst is
component dff_async_reset
  port (
    data, load, reset_a, clk, enb : in  std_logic;   -- inputs
    q                             : out std_logic);  -- output
end component;
  signal data_s,load_s,reset_a_s,clk_s,enb_s : std_logic := '0';
  signal q_s : std_logic;
begin  -- beh

  u1 : dff_async_reset port map (
    data    => data_s,
    load    => load_s,
    reset_a => reset_a_s,
    clk     => clk_s,
    enb     => enb_s,
    q       => q_s);

  tst_p: process
  begin  -- process tst_p
    clk_s <= '1';
    wait for 55 ns;
    clk_s <= '0';
    wait for 55 ns;
  end process tst_p;

 dff: process
 begin  -- process dff
   reset_a_s <= '1';
   enb_s <= '1';
   load_s <= '1';
   data_s <= '0';
   wait for 100 ns;
      reset_a_s <= '0';
   enb_s <= '1';
   load_s <= '1';
   data_s <= '0';
   wait for 100 ns;
      reset_a_s <= '0';
   enb_s <= '1';
   load_s <= '0';
   data_s <= '1';
   wait for 100 ns;
      reset_a_s <= '0';
   enb_s <= '1';
   load_s <= '0';
   data_s <= '0';
   wait for 100 ns;
  
 end process dff;
end beh;