synchronous up down counter vhdl code and test bench

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity up_down_counter is
 
  port(clk, rst_a, mode : in std_logic;  --mode=1 up counting, mode=0 down counting
        q : out std_logic_vector(3 downto 0));

end up_down_counter;

architecture archi of up_down_counter is
  signal tmp: std_logic_vector(3 downto 0);
  begin 
    process (clk, rst_a)
      begin
        if (rst_a='1') then
          tmp <= "0000";
        elsif (clk'event and clk='1') then
          if (mode='1') then
            tmp <= tmp + 1;
          else
            tmp <= tmp - 1;
          end if;
        end if;
    end process;
    q <= tmp;
end archi;


Test Bench

 library ieee;
use ieee.std_logic_1164.all;

entity up_down_counter_tst is
 
end up_down_counter_tst;

architecture beh of up_down_counter_tst is
component up_down_counter
  port(clk, rst_a,mode : in std_logic;
      q : out std_logic_vector(3 downto 0));
end component;
signal clk_s,rst_a_s,mode_s : std_logic;
signal q_s : std_logic_vector(3 downto 0);
begin  -- beh

  u1 : up_down_counter port map (
    clk   => clk_s,
    rst_a => rst_a_s,
    mode  => mode_s,
    q     => q_s);

  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 55 ns;
    clk_s <= '0';
    wait for 55 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '0';
   wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;
  end process tst;
  end beh;

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up counter with preload vhdl code and test bench

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity up_counter_sync_preload is
 
  port(clk, rst_a,load : in std_logic;
       ip: in std_logic_vector(3 downto 0);
        q : out std_logic_vector(3 downto 0));

end up_counter_sync_preload;

architecture archi of up_counter_sync_preload is
  signal tmp: std_logic_vector(3 downto 0);
  begin 
    process (clk, rst_a)
      begin
        if (rst_a='1') then
          tmp <= "0000";
       elsif (clk'event and clk='1') then
          if (load='1') then
            tmp <= ip;
           
            assert (not(tmp - tmp'last_value = "0001"))
            report "counter difer by 1"
            severity warning;
         
          else
          tmp <= tmp + '1';
          end if;

      end if;

    end process;
    q <= tmp;

end archi;

--------------------------------
Test Bench
--------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity up_counter_sync_preload_tst is
 
end up_counter_sync_preload_tst;

architecture beh of up_counter_sync_preload_tst is
component up_counter_sync_preload
  port(clk, rst_a,load : in std_logic;
       ip: in std_logic_vector(3 downto 0);
        q : out std_logic_vector(3 downto 0));
end component;
signal clk_s,rst_a_s,load_s : std_logic;
signal ip_s,q_s : std_logic_vector(3 downto 0);
begin  -- beh

  u1 : up_counter_sync_preload port map (
    clk   => clk_s,
    rst_a => rst_a_s,
    load  => load_s,
    ip    => ip_s,
    q     => q_s);

  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 55 ns;
    clk_s <= '0';
    wait for 55 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;
    rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
        rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
        rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
        rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
        rst_a_s <= '0';
    load_s <= '1';
    ip_s <= "0101";
    wait for 100 ns;
        rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
  end process tst;
  end beh;

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d flipflop with setup/hold violation, reset recovery, clock width violation and output transition vhdl code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

 
  entity d_flipflop is
   
    generic (
          constant t_setup       : time := 5 ns;      -- setup time
          constant t_hold        : time := 5 ns;      -- hold time
          constant clk_width     : time := 54 ns;     -- clock width
          constant trans_time    : time := 3 ns;      -- output transition delay
          constant rst_reco_time : time := 3 ns       -- reset recovery time
    );
      port (
          data    :in  std_logic;  -- Data input
          clk     :in  std_logic;  -- Clock input
          reset_a :in  std_logic;  -- Reset input
          q       :out std_logic;  -- Q output
          load    :in  std_logic   -- load the input
      );
  end entity;
 
  architecture beh of d_flipflop is

    signal tmp : std_logic;
   
  begin

    p1:  process (clk,reset_a,load)
           begin
          
          if (reset_a = '1') then
              tmp <= '0' after 3 ns;
          elsif(rising_edge(clk)) then
              if(load = '1') then
              tmp <= '1'after 3 ns;
              else
                tmp<= data after 3 ns;
                end if;           
          end if;
        
       end process p1;

       chk_st: process (clk)
          begin  -- process chk_st
            if(clk'event and clk='1')then
              assert (data'stable(t_setup)) report "setup violation" severity error;
            end if;
          end process chk_st;

       chk_ht: process (clk'delayed(t_hold))
          begin  -- process chk_ht
            if(clk'delayed(t_hold)'event and clk'delayed(t_hold) = '1') then
              assert (data'last_event >= t_hold) report "hold time violation" severity error;
            end if;
          end process chk_ht;
         

       chk_wd: process (clk)
          variable last_time : time := 0 ns;
          begin  -- process chk_st
            assert (now-last_time > clk_width)
              report "clock width violation"
              severity warning;
            last_time := now;        
       end process chk_wd;
      
      
      chk_rst: process (clk,reset_a)
      begin  -- process chk_rst
        if(clk'event and clk='1')then
          assert (reset_a'stable(rst_reco_time)) report "reset recovery violation" severity warning;
        end if;
      end process chk_rst;
         
       chk: process
       begin  -- process chk
              if(clk'event and clk='1')then
                 wait for trans_time;
                  if(tmp'event and tmp='0') then
                    assert (not(clk'last_event-tmp'last_event=trans_time))
                    report "output dealy for high to low transition violation"
                    severity warning;
                 elsif(tmp'event and tmp='1') then
                    assert (not(clk'last_event-tmp'last_event=trans_time))
                    report "output dealy for low to high transition violation"
                    severity warning;
                  end if;
                end if;
                wait on clk,tmp;
              end process chk;
       q<=tmp;    

end architecture;

Test bench
--------------------------

library ieee;
use ieee.std_logic_1164.all;

entity d_flipflop_tst is
 
end d_flipflop_tst;

architecture beh of d_flipflop_tst is
component d_flipflop
  port (
    data, load, reset_a, clk: in  std_logic;   -- inputs
    q                             : out std_logic);  -- output
end component;
  signal data_s,load_s,reset_a_s,clk_s : std_logic := '0';
  signal q_s : std_logic;
begin  -- beh

  u1 : d_flipflop port map (
    data    => data_s,
    load    => load_s,
    reset_a => reset_a_s,
    clk     => clk_s,
    q       => q_s);

  tst_p: process
  begin  -- process tst_p
    clk_s <= '1';
    wait for 55 ns;
    clk_s <= '0';
    wait for 55 ns;
  end process tst_p;

 dff: process
 begin  -- process dff
   reset_a_s <= '1';
   load_s <= '1';
   data_s <= '0';
   wait for 109 ns;
   reset_a_s <= '0';
   load_s <= '1';
   data_s <= '1';
   wait for 112 ns;
   reset_a_s <= '0';
   load_s <= '0';
   data_s <= '0';
   wait for 100 ns;
   reset_a_s <= '0';
   load_s <= '0';
   data_s <= '1';
   wait for 100 ns;
  
 end process dff;
end beh;

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d flipflop with asynchronous reset enable and load vhdl code and test bench

library ieee;
use ieee.std_logic_1164.all;
 
  entity dff_async_reset is
      port (
          data    :in  std_logic;  -- Data input
          clk     :in  std_logic;  -- Clock input
          reset_a :in  std_logic;  -- Reset input
          q       :out std_logic;  -- Q output
          enb     :in  std_logic;  -- enable pin
          load    :in  std_logic   -- load the input
      );
  end entity;
 
  architecture beh of dff_async_reset is
 
  begin
      process (clk,reset_a,enb,load)
           begin
          
          if (reset_a = '1') then
              q <= '0';
          elsif(rising_edge(clk) and enb ='1') then
              if(load = '1') then
              q <= '1';
              else
                q<= data;
                end if;           
          end if;
    end process;
end architecture;



test bench
---------------------

library ieee;
use ieee.std_logic_1164.all;

entity dff_async_reset_tst is
 
end dff_async_reset_tst;

architecture beh of dff_async_reset_tst is
component dff_async_reset
  port (
    data, load, reset_a, clk, enb : in  std_logic;   -- inputs
    q                             : out std_logic);  -- output
end component;
  signal data_s,load_s,reset_a_s,clk_s,enb_s : std_logic := '0';
  signal q_s : std_logic;
begin  -- beh

  u1 : dff_async_reset port map (
    data    => data_s,
    load    => load_s,
    reset_a => reset_a_s,
    clk     => clk_s,
    enb     => enb_s,
    q       => q_s);

  tst_p: process
  begin  -- process tst_p
    clk_s <= '1';
    wait for 55 ns;
    clk_s <= '0';
    wait for 55 ns;
  end process tst_p;

 dff: process
 begin  -- process dff
   reset_a_s <= '1';
   enb_s <= '1';
   load_s <= '1';
   data_s <= '0';
   wait for 100 ns;
      reset_a_s <= '0';
   enb_s <= '1';
   load_s <= '1';
   data_s <= '0';
   wait for 100 ns;
      reset_a_s <= '0';
   enb_s <= '1';
   load_s <= '0';
   data_s <= '1';
   wait for 100 ns;
      reset_a_s <= '0';
   enb_s <= '1';
   load_s <= '0';
   data_s <= '0';
   wait for 100 ns;
  
 end process dff;
end beh;

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4 bit adder/substractor using full adder

library ieee;
use ieee.std_logic_1164.all;

entity add_sub_4b_using_fa is
 
  port (
    a, b : in  std_logic_vector(3 downto 0);   -- input bits
    enb  : in  std_logic;               -- en=0=>addition  ,  en=1 =>subtract
    c    : inout std_logic_vector(3 downto 0);   -- carry
    sd    : out std_logic_vector(3 downto 0));  -- sum/diff

end add_sub_4b_using_fa;

architecture beh of add_sub_4b_using_fa is
component full_adder
    port (
    ip1 : in  std_logic;
    ip2 : in  std_logic;
    ip3 : in  std_logic;
    sum : out std_logic;
    ca  : out std_logic);
end component;

component my_xor
  port (
    ip1 : in  std_logic;
    ip2 : in  std_logic;
    op1 : out std_logic);
end component;

signal b_s: std_logic_vector(3 downto 0);

begin  -- beh

u1: my_xor port map (enb,b(0),b_s(0));
u2: my_xor port map (enb,b(1),b_s(1));
u3: my_xor port map (enb,b(2),b_s(2));
u4: my_xor port map (enb,b(3),b_s(3));
u5: full_adder port map (a(0),b_s(0),enb,sd(0),c(0));
u6: full_adder port map (a(1),b_s(1),c(0),sd(1),c(1));
u7: full_adder port map (a(2),b_s(2),c(1),sd(2),c(2));
u8: full_adder port map (a(3),b_s(3),c(2),sd(3),c(3));
 

end beh;

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4 bit magnitude comparator vhdl code

library ieee;
use ieee.std_logic_1164.all;

entity mag_comp_4b is
 
  port (
    a, b       : in  std_logic_vector(3 downto 0);       -- inputs
    ag, bg, eq : out std_logic);                         -- ag if a > b, bg if b > a, eq if a=b

end mag_comp_4b;

architecture beh of mag_comp_4b is
signal s : std_logic_vector(3 downto 0);         -- intermediate signal
begin  -- beh

s(0)<= a(0) xnor b(0);
s(1)<= a(1) xnor b(1);
s(2)<= a(2) xnor b(2);
s(3)<= a(3) xnor b(3);
eq<=s(3) and s(2) and s(1) and s(0);
ag<=(a(3) and (not b(3))) or (s(3) and a(2) and (not b(2)))or (s(3) and s(2) and a(1)and (not b(1))) or (s(3) and s(2) and s(1) and a(0) and (not b(0)));
bg<=(b(3) and (not a(3))) or (s(3) and b(2) and (not a(2)))or (s(3) and s(2) and b(1)and (not a(1))) or (s(3) and s(2) and s(1) and b(0) and (not a(0)));
end beh;

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Introduction to VHDL

Requirement of VHDL

1. Software languages are sequential Sequence of statements are significant, since theygets executed in that order.
2.  Data type are insufficient.
3. In  hardware  events  are  concurrent,  so  a  software
   language  cannot  be  used  for  describing  and
   simulating hardware.

 

Features of HDL

1. Concurrent description
2. Event Scheduling 
3. Hierarchy 
4. Flexible design methodologies 
5. Not technology specific  
6. Large design modeling is easier. 
7. Generic and attributes   
8. Supports both Synchronous and Asynchronous designs  
9. Supports three different description styles  
10. Supports wide range of abstraction levels  
11. User defined library, packages and data types. 

v





General Structure of VHDL
1.Library declaration
2. Package declaration
3. User Defined Library declaration*
4. User Defined Package declaration*
5. Entity Declaration
1. Generic Declaration*
2. Port Declaration
6. Architecture Declaration
7. Configuration Declaration*

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