library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity barrel_shifter_multi is
port (
d_in : in bit_vector (7 downto 0);
clk, rst_a : in bit;
shift_lt_rt : in bit; --0=>left shift , 1=> right shift
shift_by : in bit_vector (2 downto 0); -- 000=>parallel load, other=> shift amount
d_out : out bit_vector (7 downto 0)
);
end barrel_shifter_multi;
architecture arch of barrel_shifter_multi is
signal temp_a,temp_b,temp_c : bit_vector (7 downto 0); --signal to pass input
signal temp_sl1,temp_sl3,temp_sl2 : bit; --signal to pass shift_lt_rt value
signal temp_sby1,temp_sby2,temp_sby3 : bit_vector (2 downto 0); --signal to pass shift_by value
signal temp_4,temp_2, temp_1 : bit_vector (7 downto 0); --signal to pass output
begin -- arch
d_1: process (clk,rst_a)
begin -- process
if rst_a = '1' then -- asynchronous reset (active high)
temp_a <= "00000000";
elsif clk'event and clk = '1' then
temp_a <= d_in;
temp_sl1 <= shift_lt_rt;
temp_sby1 <= shift_by;
end if;
end process d_1;
s_4: process (clk, temp_sby1, temp_sl1, temp_a)
begin -- process
if (temp_sl1 ='1' and (temp_sby1(2) = '1')) then --shift by 4 bits
temp_4 <= temp_a ror 4;
elsif (temp_sl1 ='0' and (temp_sby1(2) = '1')) then
temp_4 <= temp_a rol 4;
else temp_4 <= temp_a;
end if;
end process s_4;
d_2: process (clk, rst_a)
begin -- process
if rst_a = '1' then -- asynchronous reset (active high)
temp_b <= "00000000";
elsif clk'event and clk = '1' then
temp_b <= temp_4;
temp_sl2 <= temp_sl1;
temp_sby2 <= temp_sby1;
end if;
end process d_2;
s_2: process (clk, temp_sby2, temp_sl2, temp_b)
begin -- process
if (temp_sl2 ='1' and (temp_sby2(1) = '1')) then --shift by 2 bits
temp_2 <= temp_b ror 2;
elsif (temp_sl2 ='0' and (temp_sby2(1) = '1' )) then
temp_2 <= temp_b rol 2;
else temp_2 <= temp_b;
end if;
end process s_2;
d_3: process (clk, rst_a)
begin -- process
if rst_a = '1' then -- asynchronous reset (active high)
temp_c <= "00000000";
elsif clk'event and clk = '1' then
temp_c <= temp_2;
temp_sl3 <= temp_sl2;
temp_sby3 <= temp_sby2;
end if;
end process d_3;
s_1: process (clk, temp_sby3, temp_sl3, temp_c)
begin -- process
if (temp_sl3 ='1' and (temp_sby3(0) = '1')) then --shift by 1 bit
temp_1 <= temp_c ror 1;
elsif (temp_sl3 ='0' and (temp_sby3(0) = '1')) then
temp_1 <= temp_c rol 1;
else temp_1 <= temp_c;
end if;
end process s_1;
d_4: process (clk, rst_a)
begin -- process
if rst_a = '1' then -- asynchronous reset (active high)
d_out <= "00000000";
elsif clk'event and clk = '1' then
d_out <= temp_1;
end if;
end process d_4;
end arch;
-----------------------------------------------
Textio code
----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
entity barrel_shifter_multi_txtio is
end barrel_shifter_multi_txtio;
architecture arch of barrel_shifter_multi_txtio is
component barrel_shifter_multi
port (
d_in : in std_logic_vector(7 downto 0); -- input vector
d_out : out std_logic_vector(7 downto 0); -- shifted output
shift_lt_rt : in std_logic; -- 0=>left_operation 1=>right_operation
shift_by : in std_logic_vector(2 downto 0); -- 000=> parallel load other=>shift amount
clk : in std_logic; -- clock signal
rst_a : in std_logic); -- reset signal
end component;
signal rst_a : std_logic;
signal shift_lt_rt: std_logic;
signal shift_by : std_logic_vector(2 downto 0);
signal d_out,d_in : std_logic_vector(7 downto 0);
signal clk : std_logic := '1'; -- clk signal
begin -- arch
u1: barrel_shifter_multi port map (
rst_a => rst_a,
clk => clk,
shift_lt_rt => shift_lt_rt,
d_in => d_in,
shift_by => shift_by,
d_out => d_out);
clk <= not clk after 50 ns;
p1: process
file infile : text open read_mode is "in_vector.txt";
file outfile : text open write_mode is "result.txt";
variable rline : line;
variable wline : line;
variable d_in_v : std_logic_vector(7 downto 0);
variable rst_a_v : std_logic;
variable shift_lt_rt_v : std_logic;
variable shift_by_v : std_logic_vector(2 downto 0);
begin -- process p1
readline(infile, rline);
write (wline, string'("rst_a"),left,15);
write (wline, string'("shift_lt_rt"),left,15);
write (wline, string'("shift_by"),left,15);
write (wline, string'("d_in"),left,15);
write (wline, string'("d_out"),left,15);
writeline(outfile, wline);
while not(endfile(infile)) loop
wait until (clk'event and clk='1');
readline(infile,rline);
read(rline, rst_a_v);
read(rline, shift_lt_rt_v);
read(rline,shift_by_v);
read(rline,d_in_v);
rst_a<=rst_a_v ;
shift_lt_rt<=shift_lt_rt_v;
shift_by<=shift_by_v ;
d_in<= d_in_v ;
write(wline,rst_a_v,left,15);
write(wline,shift_lt_rt_v,left,15);
write(wline,shift_by_v,left,15);
write(wline, d_in_v,left ,15);
write (wline,d_out,left,15);
writeline(outfile, wline);
end loop;
wait;
end process p1;
end arch;
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