Single Port RAM in VHDL using generate statement

//////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;

entity memory_sp is
 
  port (
    clk      : in  std_logic;
    address  : in  std_logic_vector(3 downto 0);   -- input address
    rd_wr    : in  std_logic;           -- read write signal  1=read 0=write
    cs       : in  std_logic;           -- chip select
    data : inout std_logic_vector(8 downto 0));  -- output data

end memory_sp;


architecture beh of memory_sp is

  type dataout is array (15 downto 0,8 downto 0) of std_logic;
  signal d1 : dataout;
  signal cs_r : std_logic_vector(15 downto 0);  -- chip enable signal
  signal addr_out : std_logic_vector(15 downto 0);  -- address from the decoder
  component dff_async_reset
      port (
          data    :in  std_logic;  -- Data input
          clk     :in  std_logic;  -- Clock input
          enb     :in  std_logic;   -- enable pin
          q       :out std_logic  -- Q output
            );
  end component;

  component deco4x16
 
  port (
    ip : in  std_logic_vector(3 downto 0);   -- input
    op : out std_logic_vector(15 downto 0));  -- output

    end component;
 
begin  -- beh
 
  addr: deco4x16 port map (address,addr_out);
  process(address,cs,rd_wr)
    begin
      cs_gen: for k in 0 to 15 loop
       
  
 end loop cs_gen;
 
 
row1: for i in 0 to 15 generate
  col: for j in 0 to 8 generate
  if (j>=0 and j<8) generate
  row1: dff_async_reset port map (data_in(i),clk,cs_r(i),d1(i,j));
  end generate;

  if (j=8) generate
  par1: dff_async_reset port map (parity_in,clk,cs_r(i),d1(i,j));
  end generate;

  end generate col;
 
end generate dff;

end beh;

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4x1 mux primitive example in verilog

///////////////////////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
primitive mux_4x1(muxed_out,sel_1,sel_0,data1,data2,data3,data4);

   output muxed_out;
   input  sel_1,sel_0;
   input  data1,data2,data3,data4;


   table

      //sel_1 sel_0 data1 data2 data3 data4

      0 0 1 ? ? ? :1;
      0 0 0 ? ? ? :0;
      0 1 ? 1 ? ? :1;
      0 1 ? 0 ? ? :0;
      1 0 ? ? 1 ? :1;
      1 0 ? ? 0 ? :0;
      1 1 ? ? ? 1 :1;
      1 1 ? ? ? 0 :0;
      ? ? 0 0 0 0 :0;
      ? ? 1 1 1 1 :1;

   endtable
endprimitive // mux_4x1
 

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D flip flop primitive in verilog example

//////////////////////////////////////////////////////////////////////////////
// Design Name : dflip flop primitive
// File Name   : d_flipflop.v
// Function    :
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
primitive d_flipflop(q,clear,clk,d);
   output q;
   reg q;
   input      d,clk,clear;
   initial q=1'b1;

   table

  //clear clk d q

     
     
      0  ?   ? : ? : 0;
      1 (01) 1 : ? : 1;
      1 (01) 0 : ? : 0;
      1 (0?) 0 : ? : 0;
      1 (0?) 1 : ? : 1;
      1 (10) ? : ? : -;
      ?  ? (??) : ? : -;
      (??)  ? ? : ? : -;

   endtable
endprimitive // d_flipflop

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Vending Machine in Verilog

 //////////////////////////////////////////////////////////////////////////////
// Design Name : Vending Machine
// File Name   : vending.v
// Function    : at 15 rupee  req op will come
// Author      : Sidharth
//Permission   : This code only for educational purpose only
//cintact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module vending(out,coin,clk,rst);
  

  output reg out;
   input [1:0] coin;
   input       clk,rst;

   reg [1:0]   state,next_state;

   parameter s0=2'd0,
           s5=2'd1,
           s10=2'd2,
           s15=2'd3;

   parameter x0=2'd0,
           x5=2'd1,
           x10=2'd2,
           x15=2'd3;

   always @ (posedge clk)
     begin
    if(rst)
      state=s0;
    else
      state=next_state;
     end

   always @ (state,coin)
     begin
    case(state)

      s0:begin
         if(coin==x5)
           begin
          next_state=s5;
          out=0;
           end
        
         else if(coin==x0)
           begin
          next_state=s0;
          out=0;
           end
        
         else if(coin==x10)
           begin
          next_state=s10;
          out=0;
           end
      end // case: s0

      s5:begin
         if(coin==x0)
           begin
          next_state=s5;
          out=0;
           end
         else if(coin==x5)
           begin
          next_state=x10;
          out=0;
           end
         else if(coin==x10)
           begin
          next_state=s15;
          out=0;
           end
      end // case: s5

      s10:begin
         if(coin==x0)
           begin
          next_state=s10;
          out=0;
           end
         else if(coin==x5)
           begin
          next_state=x15;
          out=0;
           end
         else if(coin==x10)
           begin
          next_state=s15;
          out=0;
           end
      end // case: s10

      s15:
        begin
           out=1;
           next_state=s0;
        end
        endcase
      end // always @ (state,coin)
endmodule // vending

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Simple arbiter example in verilog

 //////////////////////////////////////////////////////////////////////////////
// Design Name : Design a Priority resolver for four requests using least recently algorithm.
// File Name   : priority_resolver_new.v
// Function    : priority resolver
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//cintact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module arbiter(gnt3,gnt2,gnt1,gnt0,req3,req2,req1,req0,clk,rst);

   output reg gnt3,gnt2,gnt1,gnt0;
   input      req3,req2,req1,req0;
   input      clk,rst;

   parameter idle=3'b000;
   parameter GNT3=3'b001;
   parameter GNT2=3'b010;
   parameter GNT1=3'b011;
   parameter GNT0=3'b100;

   reg [2:0]  state,next_state;

   always @ (posedge clk)
     begin
    if(rst)
      state=idle;
    else
      state=next_state;
     end

   always @ (state,req3,req2,req1,req0)
     begin
    next_state=0;

    case (state)

      idle:begin

         if(req0)
           next_state=GNT0;
         else if(req1)
           next_state=GNT1;
         else if(req2)
           next_state=GNT2;
         else if(req3)
           next_state=GNT3;
         else
           next_state=idle;
      end // case: idle

      GNT0:begin

         if(req0)
           next_state=GNT0;
         else
           next_state=idle;
      end

      GNT1:begin
         if(req1)
           next_state=GNT1;
         else
           next_state=idle;
      end

      GNT2:begin
         if(req2)
           next_state=GNT2;
         else
           next_state=idle;
      end

      GNT3:begin
         if(req3)
           next_state=GNT3;
         else
           next_state=idle;
      end
    endcase // case (state)
     end // always @ (state,req3,req2,req1,req0)

always @ (state)
  begin
     if(state==idle)
       begin
      gnt3=0;
      gnt2=0;
      gnt1=0;
      gnt0=0;
       end
     else if(state==GNT0)
       begin
      gnt3=0;
      gnt2=0;
      gnt1=0;
      gnt0=1;
       end
     else if(state==GNT1)
       begin
      gnt3=0;
      gnt2=0;
      gnt1=1;
      gnt0=0;
       end
     else if(state==GNT2)
       begin
      gnt3=0;
      gnt2=1;
      gnt1=0;
      gnt0=0;
       end
     else if(state==GNT3)
       begin
      gnt3=1;
      gnt2=0;
      gnt1=0;
      gnt0=0;
       end
  end // always @ (state)
endmodule // arbiter


        
         
  
    

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Priority resolver with least recent algorithm in verilog

//////////////////////////////////////////////////////////////////////////////
// Design Name : Design a Priority resolver for four requests using least recently algorithm.
// File Name   : priority_resolver_new.v
// Function    : priority resolver
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//cintact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////

module priority_resolver_new (grant,req,clk,rst_a);
 
  //----------input output port declaration
  
   output  [3:0] grant;        //granted user
   input [3:0]      req;          //requesting user
   input      clk;          //clock
   input      rst_a;        //asynchronous reset



  //---------internal signal declaration
  reg [6:0] count [3:0];      //counter for priority resolving
  reg [3:0] temp;
  reg [3:0] tmp_grant;
  reg [2:0] j;
 
  assign grant = tmp_grant;
  always @(posedge clk, posedge rst_a)
  begin
    if (rst_a)
          begin
            count[0]=7'b0;
            count[1]=7'b0;
            count[2]=7'b0;
            count[3]=7'b0;
           
          end
   else if (grant[0])
        begin
                            count[0]=0;
                            count[1]=count[1]+1;
                            count[2]=count[2]+1;
                            count[3]=count[3]+1; 
         end
       else if (grant[1])
        begin
                            count[0]=count[0]+1;
                            count[1]=0;
                            count[2]=count[2]+1;
                            count[3]=count[3]+1; 
         end
         else if (grant[2])
        begin
                            count[0]=count[0]+1;
                            count[1]=count[1]+1;
                            count[2]=0;
                            count[3]=count[3]+1;
         end
         else if (grant[3])
        begin
                            count[0]=count[0]+1;
                            count[1]=count[1]+1;
                            count[2]=count[2]+1;
                            count[3]=0; 
         end
    end
       
  always @(posedge clk,posedge rst_a)
    begin
        if (rst_a)
          begin
            tmp_grant = 4'b0;
          end
       else if (count[0]==0&&count[1]==0&&count[2]==0&&count[3]==0)//intial contion priority req[0]>req[1]>req[3]>req[4]
              begin
                if (req[0])
                  begin
                  tmp_grant[0]=1'b1;
                  tmp_grant[3:1]=3'b0;
                  end
                else if (req[1])
                  begin
                  tmp_grant[0]=1'b0;
                  tmp_grant[1]=1'b1;
                  tmp_grant[2]=1'b0;
                  tmp_grant[3]=1'b0;
                  end
                else if (req[2])
                  begin
                  tmp_grant[0]=1'b0;
                  tmp_grant[1]=1'b0;
                  tmp_grant[2]=1'b1;
                  tmp_grant[3]=1'b0;
                  end
                else if (req[3])
                  begin
                  tmp_grant[0]=1'b0;
                  tmp_grant[1]=1'b0;
                  tmp_grant[2]=1'b0;
                  tmp_grant[3]=1'b1;
                  end
              end
            else                                                                                                                                     
                       if (!count[0]&&req[0])          //for req=0001
                        tmp_grant = 4'b0001;
                        else if (!count[1]&&req[1])    //for req=0010
                        tmp_grant = 4'b0010;
                        else if (!count[2]&&req[2])    //for req=0100
                        tmp_grant = 4'b0100;
                        else if (!count[3]&&req[3])    //for req=1000
                        tmp_grant = 4'b1000;
                        else
                          begin
                            tmp_grant = 4'b0;
                          if (req[0])
                              temp=count[0];
                          else if (req[1])
                            temp=count[1];
                           else if (req[2])
                           temp=count[2];
                            else if (req[3])
                             temp=count[3];
                            
                             for(j=3'b0;j<=3'b011;j=j+1) //for more than one req
                                begin
                                  
                                   if (req[j])
                                        if(temp<=count[j])
                                          begin
                                            tmp_grant=0;
                                          temp=count[j];
                                          tmp_grant[j]=1'b1;
                                          end
                                       else
                                          tmp_grant[j]=1'b0;
                                    else
                                         tmp_grant[j]=1'b0;   
                                end
                  end
          end
         endmodule  

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Synchronous FIFO with synchronous read and write with test bench in verilog

/////////////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module sync_fifo(data_out,full,empty,data_in,clk,rst_a,wr_en,rd_en);

   parameter data_width    = 4;
   parameter address_width = 4;
   parameter ram_depth     =16;


   output [data_width-1:0] data_out;
   output            full;
   output            empty;
   input [data_width-1:0]  data_in;
   input            clk;
   input            rst_a;
   input            wr_en;
   input            rd_en;


   reg [address_width-1:0]    wr_pointer;
   reg [address_width-1:0]    rd_pointer;
   reg [address_width :0]     status_count;
   reg [data_width-1:0]       data_out ;
   wire [data_width-1:0]      data_ram ;


  

   always @ (posedge clk,posedge rst_a)
     begin
    if(rst_a)
      wr_pointer = 0;
    else
      if(wr_en)
        wr_pointer = wr_pointer+1;
     end

   always @ (posedge clk,posedge rst_a)
     begin
    if(rst_a)
      rd_pointer = 0;
    else
      if(rd_en)
        rd_pointer = rd_pointer+1;
     end

   always @ (posedge clk,posedge rst_a)
     begin
    if(rst_a)
      data_out=0;
    else
      if(rd_en)
        data_out=data_ram;
     end

   always @ (posedge clk,posedge rst_a)
     begin
    if(rst_a)
      status_count = 0;
    else
      if(wr_en && !rd_en && (status_count != ram_depth))
        status_count = status_count + 1;
      else
        if(rd_en && !wr_en && (status_count != 0))
          status_count = status_count - 1;
     end // always @ (posedge clk,posedge rst_a)


   assign full = (status_count == (ram_depth-1));
   assign empty = (status_count == 0);
  
   memory_16x4 #(data_width,address_width,ram_depth) u1 (.address_1(wr_pointer),.address_2(rd_pointer),.data_1(data_in),.data_2(data_ram),.wr_en1(wr_en),.rd_en2(rd_en),.clk(clk));


endmodule // sync_fifo


---------------------------------------------------

memory_16x4
----------------------------------------------------
module memory_16x4(data_1,data_2,wr_en1,rd_en2,clk,address_1,address_2);

   parameter data_width    = 4;
   parameter address_width = 4;
   parameter ram_depth     =16;

  
   input     [data_width-1:0]      data_1;
   output     [data_width-1:0]      data_2;
   input     [address_width-1:0]   address_1;
   input     [address_width-1:0]   address_2;
   input                           wr_en1,clk,rd_en2;

  
   reg [address_width-1:0]     memory[0:ram_depth-1];
   reg [data_width-1:0]        data_2_out;
   wire [data_width-1:0]  data_2;
  

   always @(posedge clk)
     begin
    if (wr_en1)
      memory[address_1]=data_1;
     end

   always @(posedge clk)
     begin
    if (rd_en2)
      data_2_out=memory[address_2];
     end

   assign data_2=(rd_en2)?data_2_out:8'b0;

endmodule // memory_16x4
----------------------------------------------------------------

test bench
----------------------------------------------------------------

`timescale 1ns/1ps
module sync_fifo_tb;
reg [3:0]  data_in;
reg        clk,rst_a,wr_en,rd_en;
wire [3:0] data_out;
wire    full,empty;
  


sync_fifo u1 (.data_out(data_out),.full(full), .empty(empty), .wr_en(wr_en), .rd_en(rd_en), .clk(clk), .rst_a(rst_a), .data_in(data_in));

initial
begin
clk=1'b1;
forever #50 clk=~clk;
end

initial
begin
   rst_a=1'b1;
   data_in=4'b0000;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

   rst_a=1'b0;
   data_in=4'b0001;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

   rst_a=1'b0;
   data_in=4'b0010;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

   rst_a=1'b0;
   data_in=4'b0011;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

   rst_a=1'b0;
   data_in=4'b0100;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

   rst_a=1'b0;
   data_in=4'b0101;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

      rst_a=1'b0;
   data_in=4'b0110;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

      rst_a=1'b0;
   data_in=4'b0111;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;


   data_in=4'b1000;
   #100;


   data_in=4'b1001;
   #100;


   data_in=4'b1010;
   #100;


   data_in=4'b1011;
   #100;

   data_in=4'b1100;
   #100;

   data_in=4'b1101;
   #100;

   data_in=4'b1110;
   #100;

   data_in=4'b1111;
   #100;

   rd_en=1'b1;
   wr_en=1'b0;
   #1600;
  
   rst_a=1'b1;
   data_in=4'b0101;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

   rst_a=1'b0;
   data_in=4'b0101;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

   rst_a=1'b0;
   data_in=4'b0110;
   wr_en=1'b0;
   rd_en=1'b1;
   #400;

  
$stop;
end
endmodule

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