Run multiple testcases in System Verilog in Questasim

Let there are two test cases.

testcase1 and testcase2

1-First complie them using the command(for questasim)

 vlog  top.sv test_case1.sv
vlog   top.sv   test_case2.sv

2-To run them use command as given below

 vsim top +test_case1
vsim  top  +test_case2

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System Verilog Inheritance example

/*-----------------------------------BASE CLASS----------------*/

class base;
   logic [7:0] data;

   task increament(logic[7:0] temp);
     data=temp+1;
   endtask // increament

   task random();
      this.data=$random;
   endtask // random

endclass // base

/*-----------------------------------DERIVED CLASS----------------*/
class derived extends base;
   logic[7:0] packet[];
   int size;

   function new(int size);
      this.size=size;
      packet=new[size];
   endfunction // new

endclass // derived

/*-----------------------------------MODULE----------------*/

module top;

   logic[7:0] din=8'b0;
   logic[7:0] dout[];

   reg      clk=0;
   reg      reset=0;
   reg      en=0;
   int      count=0;

   initial
     begin
dout=new[pkt1.size];
     end

   always #50 clk = ~clk;

   always@(posedge clk)
     begin
if(count<pkt1.size)
 begin
    en=1;
    pkt1.increament(din);
    pkt1.packet[count]=pkt1.data;
    count+=1;
    din=din+1;
 end
else
 begin
    en=0;
    dout=pkt1.packet;
 end // else: !if(count<pkt1.size)
     end // always@ (posedge clk)

   derived pkt1 = new(5);

   endmodule

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Single Port RAM in VHDL using generate statement

//////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;

entity memory_sp is
 
  port (
    clk      : in  std_logic;
    address  : in  std_logic_vector(3 downto 0);   -- input address
    rd_wr    : in  std_logic;           -- read write signal  1=read 0=write
    cs       : in  std_logic;           -- chip select
    data : inout std_logic_vector(8 downto 0));  -- output data

end memory_sp;


architecture beh of memory_sp is

  type dataout is array (15 downto 0,8 downto 0) of std_logic;
  signal d1 : dataout;
  signal cs_r : std_logic_vector(15 downto 0);  -- chip enable signal
  signal addr_out : std_logic_vector(15 downto 0);  -- address from the decoder
  component dff_async_reset
      port (
          data    :in  std_logic;  -- Data input
          clk     :in  std_logic;  -- Clock input
          enb     :in  std_logic;   -- enable pin
          q       :out std_logic  -- Q output
            );
  end component;

  component deco4x16
 
  port (
    ip : in  std_logic_vector(3 downto 0);   -- input
    op : out std_logic_vector(15 downto 0));  -- output

    end component;
 
begin  -- beh
 
  addr: deco4x16 port map (address,addr_out);
  process(address,cs,rd_wr)
    begin
      cs_gen: for k in 0 to 15 loop
       
  
 end loop cs_gen;
 
 
row1: for i in 0 to 15 generate
  col: for j in 0 to 8 generate
  if (j>=0 and j<8) generate
  row1: dff_async_reset port map (data_in(i),clk,cs_r(i),d1(i,j));
  end generate;

  if (j=8) generate
  par1: dff_async_reset port map (parity_in,clk,cs_r(i),d1(i,j));
  end generate;

  end generate col;
 
end generate dff;

end beh;

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4x1 mux primitive example in verilog

///////////////////////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
primitive mux_4x1(muxed_out,sel_1,sel_0,data1,data2,data3,data4);

   output muxed_out;
   input  sel_1,sel_0;
   input  data1,data2,data3,data4;


   table

      //sel_1 sel_0 data1 data2 data3 data4

      0 0 1 ? ? ? :1;
      0 0 0 ? ? ? :0;
      0 1 ? 1 ? ? :1;
      0 1 ? 0 ? ? :0;
      1 0 ? ? 1 ? :1;
      1 0 ? ? 0 ? :0;
      1 1 ? ? ? 1 :1;
      1 1 ? ? ? 0 :0;
      ? ? 0 0 0 0 :0;
      ? ? 1 1 1 1 :1;

   endtable
endprimitive // mux_4x1
 

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D flip flop primitive in verilog example

//////////////////////////////////////////////////////////////////////////////
// Design Name : dflip flop primitive
// File Name   : d_flipflop.v
// Function    :
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
primitive d_flipflop(q,clear,clk,d);
   output q;
   reg q;
   input      d,clk,clear;
   initial q=1'b1;

   table

  //clear clk d q

     
     
      0  ?   ? : ? : 0;
      1 (01) 1 : ? : 1;
      1 (01) 0 : ? : 0;
      1 (0?) 0 : ? : 0;
      1 (0?) 1 : ? : 1;
      1 (10) ? : ? : -;
      ?  ? (??) : ? : -;
      (??)  ? ? : ? : -;

   endtable
endprimitive // d_flipflop

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Vending Machine in Verilog

 //////////////////////////////////////////////////////////////////////////////
// Design Name : Vending Machine
// File Name   : vending.v
// Function    : at 15 rupee  req op will come
// Author      : Sidharth
//Permission   : This code only for educational purpose only
//cintact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module vending(out,coin,clk,rst);
  

  output reg out;
   input [1:0] coin;
   input       clk,rst;

   reg [1:0]   state,next_state;

   parameter s0=2'd0,
           s5=2'd1,
           s10=2'd2,
           s15=2'd3;

   parameter x0=2'd0,
           x5=2'd1,
           x10=2'd2,
           x15=2'd3;

   always @ (posedge clk)
     begin
    if(rst)
      state=s0;
    else
      state=next_state;
     end

   always @ (state,coin)
     begin
    case(state)

      s0:begin
         if(coin==x5)
           begin
          next_state=s5;
          out=0;
           end
        
         else if(coin==x0)
           begin
          next_state=s0;
          out=0;
           end
        
         else if(coin==x10)
           begin
          next_state=s10;
          out=0;
           end
      end // case: s0

      s5:begin
         if(coin==x0)
           begin
          next_state=s5;
          out=0;
           end
         else if(coin==x5)
           begin
          next_state=x10;
          out=0;
           end
         else if(coin==x10)
           begin
          next_state=s15;
          out=0;
           end
      end // case: s5

      s10:begin
         if(coin==x0)
           begin
          next_state=s10;
          out=0;
           end
         else if(coin==x5)
           begin
          next_state=x15;
          out=0;
           end
         else if(coin==x10)
           begin
          next_state=s15;
          out=0;
           end
      end // case: s10

      s15:
        begin
           out=1;
           next_state=s0;
        end
        endcase
      end // always @ (state,coin)
endmodule // vending

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Simple arbiter example in verilog

 //////////////////////////////////////////////////////////////////////////////
// Design Name : Design a Priority resolver for four requests using least recently algorithm.
// File Name   : priority_resolver_new.v
// Function    : priority resolver
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//cintact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module arbiter(gnt3,gnt2,gnt1,gnt0,req3,req2,req1,req0,clk,rst);

   output reg gnt3,gnt2,gnt1,gnt0;
   input      req3,req2,req1,req0;
   input      clk,rst;

   parameter idle=3'b000;
   parameter GNT3=3'b001;
   parameter GNT2=3'b010;
   parameter GNT1=3'b011;
   parameter GNT0=3'b100;

   reg [2:0]  state,next_state;

   always @ (posedge clk)
     begin
    if(rst)
      state=idle;
    else
      state=next_state;
     end

   always @ (state,req3,req2,req1,req0)
     begin
    next_state=0;

    case (state)

      idle:begin

         if(req0)
           next_state=GNT0;
         else if(req1)
           next_state=GNT1;
         else if(req2)
           next_state=GNT2;
         else if(req3)
           next_state=GNT3;
         else
           next_state=idle;
      end // case: idle

      GNT0:begin

         if(req0)
           next_state=GNT0;
         else
           next_state=idle;
      end

      GNT1:begin
         if(req1)
           next_state=GNT1;
         else
           next_state=idle;
      end

      GNT2:begin
         if(req2)
           next_state=GNT2;
         else
           next_state=idle;
      end

      GNT3:begin
         if(req3)
           next_state=GNT3;
         else
           next_state=idle;
      end
    endcase // case (state)
     end // always @ (state,req3,req2,req1,req0)

always @ (state)
  begin
     if(state==idle)
       begin
      gnt3=0;
      gnt2=0;
      gnt1=0;
      gnt0=0;
       end
     else if(state==GNT0)
       begin
      gnt3=0;
      gnt2=0;
      gnt1=0;
      gnt0=1;
       end
     else if(state==GNT1)
       begin
      gnt3=0;
      gnt2=0;
      gnt1=1;
      gnt0=0;
       end
     else if(state==GNT2)
       begin
      gnt3=0;
      gnt2=1;
      gnt1=0;
      gnt0=0;
       end
     else if(state==GNT3)
       begin
      gnt3=1;
      gnt2=0;
      gnt1=0;
      gnt0=0;
       end
  end // always @ (state)
endmodule // arbiter


        
         
  
    

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