Universal shifter in verilog with test bench

/////////////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module uni_shift_8b(op,clk,rst_a, load,sh_ro_lt_rt,ip);
  output reg [7:0] op;
  input load;
  input [1:0] sh_ro_lt_rt;
  input [7:0] ip;
  input clk, rst_a;
 
  reg [7:0]temp;
 
 
 
  always @(posedge clk or posedge rst_a)
   begin
     if (rst_a)
      
       op = 0;
     
     else   
       case(load)
         1'b1:
          begin                            //Load Input
            temp = ip;
          //  op = temp;
          end
         1'b0:                             //Operation
          case (sh_ro_lt_rt)
            2'b00:  op = temp<<1;     //Left Shift
            2'b01:  op = temp>>1;     //Right Shift
            2'b10:  op = {temp[6:0],temp[7]}; //Rotate Left
            2'b11:  op = {temp[0], temp[7:1]};  //Rotate Right
                  
            default: $display("Invalid Shift Control Input");
          endcase
     
       
        
        default: $display("Invalid Load Control Input");
        endcase
  
    end
   
  endmodule
         
   -----------------------------------------------------------

test bench
----------------------------------------------------------------
`timescale 1ns/1ps

module uni_shift_8b_tst;
  reg [7:0] ip;
  reg [1:0] sh_ro_lt_rt;
  reg         load,rst_a,clk;
  wire [7:0] op;


   uni_shift_8b u1 (.op(op), .ip(ip), .sh_ro_lt_rt(sh_ro_lt_rt), .load(load) , .rst_a(rst_a) , .clk(clk));

initial
  begin
     clk=1'b1;
     forever #50 clk=~clk;  
  end
 
   initial
     begin
    ip = 8'b11001100;
    rst_a = 1'b1;
    load = 1'b1;
    sh_ro_lt_rt = 2'b00;
    #100;
   
    ip = 8'b10001100;
    rst_a = 1'b0;
    load = 1'b1;
    sh_ro_lt_rt = 2'b01;
    #100;
   
    ip = 8'b11001100;

    load = 1'b0;
    sh_ro_lt_rt = 2'b01;
    #100;
   
    ip = 8'b10101101;
   
    load = 1'b1;
    sh_ro_lt_rt = 2'b01;
    #100;
   
    ip = 8'b11001101;

    load = 1'b0;
    sh_ro_lt_rt = 2'b01;
    #100;

    ip = 8'b11101100;
    load = 1'b1;
    sh_ro_lt_rt = 2'b10;
    #100;

    ip = 8'b11110000;
    load = 1'b0;
    sh_ro_lt_rt = 2'b10;
    #100;

    ip = 8'b11001100;
    load = 1'b1;
    sh_ro_lt_rt = 2'b11;
    #100;

    ip = 8'b11001101;
    load = 1'b0;
    sh_ro_lt_rt = 2'b11;
    #100;
   
    ip = 8'b11001000;
    load = 1'b1;
    sh_ro_lt_rt = 2'b11;
    #100;
    $stop;
     end // initial begin
   endmodule
   
  

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ALU in verilog with test bench

/////////////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module alu (op,a,b,c_log_arith);

  output reg [3:0] op;     //output of alu
   input [3:0]        a,b;    //inputs to alu
   input [1:0] c_log_arith;//control signal for logical/arithmatic operation

   always @(*)

    begin
    case (c_log_arith)
      2'b00 : begin op = a + b; $display("Addition operation"); end
      2'b01 : begin op = a - b; $display("Subtraction operation"); end
      2'b10 : begin op = ~(a & b); $display("logical NAND operation"); end
      2'b11 : begin op = a ^ b; $display("Logical XOR operation"); end

      default:op = 4'bXXXX;
    endcase

    end


endmodule

----------------------------------------------

test bench
-----------------------------------------------
`timescale 1ns/1ps
module alu_tst;
  reg [3:0] a,b;
  reg [1:0] c_log_arith;
  wire [3:0] op;


   alu u1 (.op(op), .a(a), .b(b) , .c_log_arith(c_log_arith));


   initial
     begin
   
    a=4'b0011;
    b=4'b1101;
    c_log_arith=2'b00;
    #100;
   
    a=4'b1101;
    b=4'b1111;
    c_log_arith=2'b01;
    #100;
   
    a=4'b0011;
    b=4'b1100;
    c_log_arith=2'b10;
    #100;
   
    a=4'b1110;
    b=4'b0100;
    c_log_arith=2'b11;
    #100;

    a=4'b0111;
    b=4'b1001;
    c_log_arith=2'b00;
    #100;
   
    a=4'b1111;
    b=4'b1111;
    c_log_arith=2'b01;
    #100;
   
    a=4'b1011;
    b=4'b1101;
    c_log_arith=2'b10;
    #100;
   
    a=4'b1110;
    b=4'b0111;
    c_log_arith=2'b11;
    #100
    $stop;
     end
   endmodule
   
  

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Finite state machine -pattern checker in vhdl

When a certain serial binary communication
channel is operating correctly, all blocks of 0's are
of even length and all blocks of 1's are of odd
length. The machine should produce and output
pulse z = 1 whenever discrepancy from the above
pattern is detected.
Example:
X : 0 0 1 0 0 0 1 1 1 0 1 1 0 0…
Z : 0 0 0 0 0 0 1 0 0 0 1 0 1 0…



library ieee;
use ieee.std_logic_1164.all;

entity fsm_prob3 is
 
  port (
    clk                : in  std_logic;
    rst_a              : in  std_logic;
    ip                 : in  std_logic;
    op                 : out std_logic);

end fsm_prob3;

architecture fsm_arch of fsm_prob3 is

  type state_t is (s_idle,s1 ,s2, s3);
  signal present_state : state_t;
  signal next_state : state_t;
 
begin  -- fsm_arch

p1: process (present_state,ip)
begin  -- process p1

  case present_state is

  when s_idle =>
    if ip='1' then
      op <= '0';
      next_state <= s1;
      else
        op <= '0';
        next_state <= s2;
    end if;

  when s1 =>
    if ip = '1' then
      op <= '0';
      next_state <= s3;
      else
        op<='0';
        next_state <= s2;
    end if;

  when s2 =>
    if ip = '1' then
      op <= '1';
      next_state <= s1;
      else
        op <= '0';
        next_state <= s_idle;
    end if;

  when s3 =>
    if ip = '1' then
      op <= '0';
      next_state <= s1;
      else
        op <= '1';
        next_state <= s2;
    end if; 
  end case;
end process p1;

seq_p: process (clk, rst_a)
begin  -- process seq_p
  if rst_a = '1' then                   -- asynchronous reset (active high)
   
    present_state <= s_idle;
  elsif clk'event and clk = '1' then    -- rising clock edge
   
    present_state <= next_state;
  end if;
end process seq_p;
 

end fsm_arch;

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User defined package in vhdl example

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

package combo_logic is

  function mux2x1 (d1,d2,sel : std_logic) return std_logic;
  function parity_chk (signal d_in : std_logic_vector) return std_logic;
  function left_shift (signal d_in : std_logic_vector; signal shift_by : integer)  return bit_vector;
  function right_shift (signal d_in : std_logic_vector; signal shift_by : integer) return bit_vector; 
 
end combo_logic;


package body combo_logic is
--------------------------------------------------------------------------------
--function body for mux2x1
-------------------------------------------------------------------------------
 function mux2x1 (d1,d2,sel : std_logic) return std_logic
   is begin

        if(sel='0')then

        return d1;

        else

        return d2;
     end if;
 end mux2x1;
 ------------------------------------------------------------------------------
 --function body for parity_chk
 ------------------------------------------------------------------------------

 function parity_chk (signal d_in : std_logic_vector) return std_logic
   is
   constant len : integer:=(d_in)'length-1;
   variable tmp : std_logic:='0';
 begin
   for i in len loop
     tmp:=tmp xor d_in(i);
   end loop;  -- i
  
 return tmp;
 end function;
-------------------------------------------------------------------------------
--function body for left_shift
-------------------------------------------------------------------------------

 function left_shift (signal d_in : std_logic_vector; signal shift_by : integer)  return bit_vector
   is
   constant len : integer:=d_in'length;
   variable tmp : bit_vector(len-1 downto 0):=to_bitvector(d_in);
  
 begin
  assert len>shift_by report "shift_by greater than length of input data" severity error;
  tmp:=tmp rol shift_by;
  return tmp;
 end function;
-------------------------------------------------------------------------------
--function body for right_shift
-------------------------------------------------------------------------------

 function right_shift (signal d_in : std_logic_vector; signal shift_by : integer)  return bit_vector
   is
   constant len : integer:=d_in'length;
   variable tmp : bit_vector(len-1 downto 0):=to_bitvector(d_in);
 begin
   assert len>shift_by report "shift_by greater than length of input data" severity error;
  tmp:=tmp ror shift_by;
  return tmp;
 end function;

end combo_logic;

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4 bit full adder verilog code

module full_adder_4b(sum,cout,a,b,cin);
   output [3:0] sum;
   output     cout;
   input [3:0]     a,b;
   input     cin;

   full_adder f1 (sum[0], cout0, a[0], b[0], cin);
   full_adder f2 (sum[1], cout1, a[1], b[1], cout0);
   full_adder f3 (sum[2], cout2, a[2], b[2], cout1);
   full_adder f4 (sum[3], cout, a[3], b[3], cout2);

   endmodule

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D latch verilog code

module d_latch(q, q_bar, d_in, enb);

   output q,q_bar;
   input  d_in;
   input  enb;

   nand g1 (s, d_in, enb),
        g2 (r, d_bar, enb);
  
   not g3 (d_bar,d_in);
   nand g4 (q, s, q_bar);
   nand g5 (q_bar, r, q);

   endmodule
  

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4:16 decoder verilog code

module decoder_4x16 (d_out, d_in);
   output [15:0] d_out;
   input [3:0]      d_in;
   parameter tmp = 16'b0000_0000_0000_0001;
  


assign d_out = (d_in == 4'b0000) ? tmp   :
               (d_in == 4'b0001) ? tmp<<1:
               (d_in == 4'b0010) ? tmp<<2:
           (d_in == 4'b0011) ? tmp<<3:
           (d_in == 4'b0100) ? tmp<<4:
           (d_in == 4'b0101) ? tmp<<5:
           (d_in == 4'b0110) ? tmp<<6:
           (d_in == 4'b0111) ? tmp<<7:
           (d_in == 4'b1000) ? tmp<<8:
           (d_in == 4'b1001) ? tmp<<9:
           (d_in == 4'b1010) ? tmp<<10:
           (d_in == 4'b1011) ? tmp<<11:
           (d_in == 4'b1100) ? tmp<<12:
           (d_in == 4'b1101) ? tmp<<13:
           (d_in == 4'b1110) ? tmp<<14:
           (d_in == 4'b1111) ? tmp<<15: 16'bxxxx_xxxx_xxxx_xxxx;
            
              
             endmodule

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