Single Port RAM in VHDL using generate statement

//////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;

entity memory_sp is
 
  port (
    clk      : in  std_logic;
    address  : in  std_logic_vector(3 downto 0);   -- input address
    rd_wr    : in  std_logic;           -- read write signal  1=read 0=write
    cs       : in  std_logic;           -- chip select
    data : inout std_logic_vector(8 downto 0));  -- output data

end memory_sp;


architecture beh of memory_sp is

  type dataout is array (15 downto 0,8 downto 0) of std_logic;
  signal d1 : dataout;
  signal cs_r : std_logic_vector(15 downto 0);  -- chip enable signal
  signal addr_out : std_logic_vector(15 downto 0);  -- address from the decoder
  component dff_async_reset
      port (
          data    :in  std_logic;  -- Data input
          clk     :in  std_logic;  -- Clock input
          enb     :in  std_logic;   -- enable pin
          q       :out std_logic  -- Q output
            );
  end component;

  component deco4x16
 
  port (
    ip : in  std_logic_vector(3 downto 0);   -- input
    op : out std_logic_vector(15 downto 0));  -- output

    end component;
 
begin  -- beh
 
  addr: deco4x16 port map (address,addr_out);
  process(address,cs,rd_wr)
    begin
      cs_gen: for k in 0 to 15 loop
       
  
 end loop cs_gen;
 
 
row1: for i in 0 to 15 generate
  col: for j in 0 to 8 generate
  if (j>=0 and j<8) generate
  row1: dff_async_reset port map (data_in(i),clk,cs_r(i),d1(i,j));
  end generate;

  if (j=8) generate
  par1: dff_async_reset port map (parity_in,clk,cs_r(i),d1(i,j));
  end generate;

  end generate col;
 
end generate dff;

end beh;

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Sequential multiplier using booth algorithm in verilog with test bench

//-----------------------------------------------------
// Design Name : Design and verify a sequential multiplier using Booths algorithm
// File Name   : booth_seq_multi.v
// Function    : Signed multiplication
// Author      :  Sidharth(DVLSI 31)
//-----------------------------------------------------
module booth_seq_multi(op,clk,rst_a,load,a,b);

   //parameter declaration-----------------------------
   parameter ip1_data_width = 4;
   parameter ip2_data_width = 4;
   parameter op_data_width  = ip1_data_width + ip2_data_width;
   parameter reg_data_width =ip1_data_width + ip2_data_width + 1;
  
   integer i;
  

   //input output declaration--------------------------
   output reg [op_data_width-1:0] op;
   input                   clk,rst_a,load;
   input [ip1_data_width-1:0]       a;
   input [ip2_data_width-1:0]       b;
  
   //register declaration------------------------------
   reg [reg_data_width-1:0]     tmp_a,tmp_s,tmp_p;
   reg [ip1_data_width-1:0]     tmp_abar,tmp_a2s,tmp_a1,tmp_b;
  
   
  always @(posedge clk)
    begin
       if(load)                  // Register the inputs
     begin
        tmp_a1=a;
        tmp_b=b;
     end
    end
  
   always @ (posedge clk,posedge rst_a)
   begin
    if(rst_a)
      op=0;
    else
      begin
       if(~load)
         begin
        tmp_abar= ~ tmp_a1;
        tmp_a2s = (tmp_abar + 1);   
        tmp_a={tmp_a1,5'b00000};
        tmp_s={tmp_a2s,5'b00000};
        tmp_p={4'b0000,tmp_b,1'b0};
       
        for(i=0;i<4;i=i+1)
          begin
             case(tmp_p[1:0])

               2'b00 : tmp_p = {tmp_p[8],tmp_p[8:1]};
               2'b01 :begin tmp_p =tmp_p + tmp_a;
                            tmp_p = {tmp_p[8],tmp_p[8:1]};
                      end
               2'b10 :begin tmp_p = tmp_p + tmp_s;
                            tmp_p = {tmp_p[8],tmp_p[8:1]};
                          end
               2'b11 : tmp_p = {tmp_p[8],tmp_p[8:1]};
               default: tmp_p = 9'bx;
             endcase // case (tmp_p[1:0])
          end // for (i=0;i<4;i=i+1)

              op=tmp_p[8:1];
         end // if (~load)
       end // else: !if(rst_a)
     end
endmodule // booth_seq_multi

----------------------------------------------------------------

test bench
----------------------------------------------------------------
`timescale 1ns/1ps
module booth_seq_multi_tb;
reg [3:0] a,b;
reg load,clk,rst_a;
wire [7:0] op;


booth_seq_multi u1 (.op(op), .a(a), .b(b), .load(load), .clk(clk), .rst_a(rst_a));

initial
begin
clk=1'b1;
forever #50 clk=~clk;
end

initial
begin
rst_a=1'b1;
a=4'b1010;
b=4'b0010;
load=1'b1;

#100;
rst_a=1'b0;
a=4'b1110;
b=4'b0101;
load=1'b1;

#100;
a=4'b1000;
b=4'b0101;
load=1'b0;
rst_a=1'b0;
#100;
a=4'b1010;
b=4'b1111;
load=1'b1;
rst_a=1'b0;
#100;
a=4'b1111;
b=4'b1001;
load=1'b1;
rst_a=1'b0;

#100;
a=4'b1011;
b=4'b0100;
load=1'b0;
rst_a=1'b0;
#100;

a=4'b1010;
b=4'b1000;
load=1'b1;
rst_a=1'b0;
#100;

a=4'b1000;
b=4'b0101;
load=1'b0;
rst_a=1'b0;
#100;


$stop;
end
endmodule

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Finite state machine -pattern checker in vhdl

When a certain serial binary communication
channel is operating correctly, all blocks of 0's are
of even length and all blocks of 1's are of odd
length. The machine should produce and output
pulse z = 1 whenever discrepancy from the above
pattern is detected.
Example:
X : 0 0 1 0 0 0 1 1 1 0 1 1 0 0…
Z : 0 0 0 0 0 0 1 0 0 0 1 0 1 0…



library ieee;
use ieee.std_logic_1164.all;

entity fsm_prob3 is
 
  port (
    clk                : in  std_logic;
    rst_a              : in  std_logic;
    ip                 : in  std_logic;
    op                 : out std_logic);

end fsm_prob3;

architecture fsm_arch of fsm_prob3 is

  type state_t is (s_idle,s1 ,s2, s3);
  signal present_state : state_t;
  signal next_state : state_t;
 
begin  -- fsm_arch

p1: process (present_state,ip)
begin  -- process p1

  case present_state is

  when s_idle =>
    if ip='1' then
      op <= '0';
      next_state <= s1;
      else
        op <= '0';
        next_state <= s2;
    end if;

  when s1 =>
    if ip = '1' then
      op <= '0';
      next_state <= s3;
      else
        op<='0';
        next_state <= s2;
    end if;

  when s2 =>
    if ip = '1' then
      op <= '1';
      next_state <= s1;
      else
        op <= '0';
        next_state <= s_idle;
    end if;

  when s3 =>
    if ip = '1' then
      op <= '0';
      next_state <= s1;
      else
        op <= '1';
        next_state <= s2;
    end if; 
  end case;
end process p1;

seq_p: process (clk, rst_a)
begin  -- process seq_p
  if rst_a = '1' then                   -- asynchronous reset (active high)
   
    present_state <= s_idle;
  elsif clk'event and clk = '1' then    -- rising clock edge
   
    present_state <= next_state;
  end if;
end process seq_p;
 

end fsm_arch;

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User defined package in vhdl example

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

package combo_logic is

  function mux2x1 (d1,d2,sel : std_logic) return std_logic;
  function parity_chk (signal d_in : std_logic_vector) return std_logic;
  function left_shift (signal d_in : std_logic_vector; signal shift_by : integer)  return bit_vector;
  function right_shift (signal d_in : std_logic_vector; signal shift_by : integer) return bit_vector; 
 
end combo_logic;


package body combo_logic is
--------------------------------------------------------------------------------
--function body for mux2x1
-------------------------------------------------------------------------------
 function mux2x1 (d1,d2,sel : std_logic) return std_logic
   is begin

        if(sel='0')then

        return d1;

        else

        return d2;
     end if;
 end mux2x1;
 ------------------------------------------------------------------------------
 --function body for parity_chk
 ------------------------------------------------------------------------------

 function parity_chk (signal d_in : std_logic_vector) return std_logic
   is
   constant len : integer:=(d_in)'length-1;
   variable tmp : std_logic:='0';
 begin
   for i in len loop
     tmp:=tmp xor d_in(i);
   end loop;  -- i
  
 return tmp;
 end function;
-------------------------------------------------------------------------------
--function body for left_shift
-------------------------------------------------------------------------------

 function left_shift (signal d_in : std_logic_vector; signal shift_by : integer)  return bit_vector
   is
   constant len : integer:=d_in'length;
   variable tmp : bit_vector(len-1 downto 0):=to_bitvector(d_in);
  
 begin
  assert len>shift_by report "shift_by greater than length of input data" severity error;
  tmp:=tmp rol shift_by;
  return tmp;
 end function;
-------------------------------------------------------------------------------
--function body for right_shift
-------------------------------------------------------------------------------

 function right_shift (signal d_in : std_logic_vector; signal shift_by : integer)  return bit_vector
   is
   constant len : integer:=d_in'length;
   variable tmp : bit_vector(len-1 downto 0):=to_bitvector(d_in);
 begin
   assert len>shift_by report "shift_by greater than length of input data" severity error;
  tmp:=tmp ror shift_by;
  return tmp;
 end function;

end combo_logic;

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Barrel shifter with multi cycle and textio vhdl code

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity barrel_shifter_multi is
 
  port (
    d_in          : in bit_vector (7 downto 0);
    clk, rst_a    : in bit;
    shift_lt_rt   : in bit;                     --0=>left shift , 1=> right shift
    shift_by      : in bit_vector (2 downto 0); -- 000=>parallel load, other=> shift amount
    d_out      : out bit_vector (7 downto 0)
    );

end barrel_shifter_multi;

architecture arch of barrel_shifter_multi is
signal temp_a,temp_b,temp_c           : bit_vector (7 downto 0);     --signal to pass input
signal temp_sl1,temp_sl3,temp_sl2     : bit;                         --signal to pass shift_lt_rt value
signal temp_sby1,temp_sby2,temp_sby3  : bit_vector (2 downto 0);     --signal to pass shift_by value
signal temp_4,temp_2, temp_1          : bit_vector (7 downto 0);     --signal to pass output
begin  -- arch

  d_1: process (clk,rst_a)
  begin  -- process
    if rst_a = '1' then                   -- asynchronous reset (active high)
      temp_a <= "00000000";
    elsif clk'event and clk = '1' then
      temp_a <= d_in;
      temp_sl1 <= shift_lt_rt;
      temp_sby1 <= shift_by;
    end if;
  end process d_1;

  s_4: process (clk, temp_sby1, temp_sl1, temp_a)
  begin  -- process
    if (temp_sl1 ='1' and (temp_sby1(2) = '1')) then     --shift by 4 bits
      temp_4 <= temp_a ror 4;
      elsif (temp_sl1 ='0' and (temp_sby1(2) = '1')) then
      temp_4 <= temp_a rol 4;
      else temp_4 <= temp_a;
    end if;
  end process s_4;

 d_2: process (clk, rst_a)
  begin  -- process
    if rst_a = '1' then                   -- asynchronous reset (active high)
      temp_b <= "00000000";
    elsif clk'event and clk = '1' then
      temp_b <= temp_4;
      temp_sl2 <= temp_sl1;
      temp_sby2 <= temp_sby1;
    end if;
  end process d_2;

 s_2:  process (clk, temp_sby2, temp_sl2, temp_b)
  begin  -- process
    if (temp_sl2 ='1' and (temp_sby2(1) = '1')) then          --shift by 2 bits
      temp_2 <= temp_b ror 2;
      elsif (temp_sl2 ='0' and (temp_sby2(1) = '1' )) then
      temp_2 <= temp_b rol 2;
      else temp_2 <= temp_b;
    end if;
  end process s_2;

 
  d_3: process (clk, rst_a)
  begin  -- process
    if rst_a = '1' then                   -- asynchronous reset (active high)
      temp_c <= "00000000";
    elsif clk'event and clk = '1' then
      temp_c <= temp_2;
      temp_sl3 <= temp_sl2;
      temp_sby3 <= temp_sby2;
    end if;
  end process d_3;

  s_1:  process (clk, temp_sby3, temp_sl3, temp_c)
  begin  -- process
    if (temp_sl3 ='1' and (temp_sby3(0) = '1')) then        --shift by 1 bit
      temp_1 <= temp_c ror 1;
      elsif (temp_sl3 ='0' and (temp_sby3(0) = '1')) then
      temp_1 <= temp_c rol 1;
      else temp_1 <= temp_c;
    end if;
  end process s_1;
 
  d_4: process (clk, rst_a)
  begin  -- process
    if rst_a = '1' then                   -- asynchronous reset (active high)
      d_out <= "00000000";
    elsif clk'event and clk = '1' then
      d_out <= temp_1;
    end if;
  end process d_4;

end arch;
-----------------------------------------------

Textio code
----------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;

library std;
use std.textio.all;

entity barrel_shifter_multi_txtio is
 
end barrel_shifter_multi_txtio;

architecture arch of barrel_shifter_multi_txtio is

  component barrel_shifter_multi
  port (
    d_in        : in  std_logic_vector(7 downto 0);   -- input vector
    d_out       : out std_logic_vector(7 downto 0);   -- shifted output
    shift_lt_rt : in  std_logic;                      -- 0=>left_operation 1=>right_operation
    shift_by    : in  std_logic_vector(2 downto 0);   -- 000=> parallel load other=>shift amount
    clk         : in  std_logic;                      -- clock signal
    rst_a       : in  std_logic);                     -- reset signal

  end component;

signal rst_a : std_logic;
signal shift_lt_rt: std_logic;
signal shift_by : std_logic_vector(2 downto 0);
signal d_out,d_in : std_logic_vector(7 downto 0);
signal clk : std_logic := '1';          -- clk signal

begin  -- arch

u1: barrel_shifter_multi port map (
  rst_a      => rst_a,
  clk        => clk,
  shift_lt_rt   => shift_lt_rt,
  d_in       => d_in,
  shift_by   => shift_by,
  d_out     => d_out);

clk <= not clk after 50 ns;

p1: process
 
  file infile         : text open read_mode is "in_vector.txt";
  file outfile        : text open write_mode is "result.txt";
  variable rline      : line;
  variable wline      : line;
  variable d_in_v     : std_logic_vector(7 downto 0);
  variable rst_a_v    : std_logic;
  variable shift_lt_rt_v : std_logic;
  variable shift_by_v : std_logic_vector(2 downto 0);
 
begin  -- process p1
readline(infile, rline);
write (wline, string'("rst_a"),left,15);
write (wline, string'("shift_lt_rt"),left,15);
write (wline, string'("shift_by"),left,15);
write (wline, string'("d_in"),left,15);
write (wline, string'("d_out"),left,15);

writeline(outfile, wline);

 while not(endfile(infile)) loop
   wait until (clk'event and clk='1');
   readline(infile,rline);
   read(rline, rst_a_v);
   read(rline, shift_lt_rt_v);
   read(rline,shift_by_v);
   read(rline,d_in_v);
 
   rst_a<=rst_a_v ;
   shift_lt_rt<=shift_lt_rt_v;
   shift_by<=shift_by_v ;
   d_in<= d_in_v ;
 
   write(wline,rst_a_v,left,15);
   write(wline,shift_lt_rt_v,left,15);
   write(wline,shift_by_v,left,15);
   write(wline, d_in_v,left ,15);
   write (wline,d_out,left,15);
   writeline(outfile, wline);
 end loop;
 wait;
end process p1;
end arch;

---------------------------------------------------------

in_vector
------------
rst_a shift_lt_rt shift_by d_in
1 0 000 00000000
0 0 001 11110000
0 0 011 11100000
0 0 101 10000111
0 0 110 10000111
0 1 110 10000111
0 1 010 10000111
0 1 101 11100111
0 1 010 10000111
0 1 100 10000111
0 0 100 10010111
0 1 100 10110111
0 0 010 10010111
0 1 100 10011111
0 1 001 10101101
0 0 011 10101101
0 0 110 11100010
0 1 101 11100010
0 0 011 10101101
0 1 010 11100010
0 0 001 11100010
1 0 001 11100010
0 1 001 11110000
0 1 010 11100000
0 1 000 11100000
0 1 000 11110000
0 1 010 11100000
0 1 010 11100000

out_vector
---------------------
rst_a          shift_lt_rt    shift_by       d_in           d_out         
1              0              000            00000000       00000000      
0              0              001            11110000       00000000      
0              0              011            11100000       00000000      
0              0              101            10000111       00000000      
0              0              110            10000111       00000000      
0              1              110            10000111       11100001      
0              1              010            10000111       00000111      
0              1              101            11100111       11110000      
0              1              010            10000111       11100001      
0              1              100            10000111       00011110      
0              0              100            10010111       11100001      
0              1              100            10110111       00111111      
0              0              010            10010111       11100001      
0              1              100            10011111       01111000      
0              1              001            10101101       01111001      
0              0              011            10101101       01111011      
0              0              110            11100010       01011110      
0              1              101            11100010       11111001      
0              0              011            10101101       11010110      
0              1              010            11100010       01101101      
0              0              001            11100010       10111000      
1              0              001            11100010       00010111      
0              1              001            11110000       00000000      
0              1              010            11100000       00000000      
0              1              000            11100000       00000000      
0              1              000            11110000       00000000      
0              1              010            11100000       01111000      
0              1              010            11100000       00111000      

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Vhdl code for barrel shifter with single cycle

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity barrel_shifter is
 
  port (
    d_in        : in  bit_vector(7 downto 0);   -- input vector
    d_out       : out bit_vector(7 downto 0);   -- shifted output
    shift_lt_rt : in  bit;                      -- 0=>left_operation 1=>right_operation
    shift_by    : in  bit_vector(2 downto 0);   -- 000=> parallel load other=>shift amount
    clk         : in  bit;                      -- clock signal
    rst_a       : in  bit);                     -- reset signal

end barrel_shifter;

architecture beh of barrel_shifter is

begin  -- beh
 p1: process (clk,rst_a,shift_by,shift_lt_rt)
variable x,y : bit_vector(7 downto 0);
variable ctrl0,ctrl1,ctrl2 : bit_vector(1 downto 0);
 begin  -- process p1
ctrl0:=shift_by(0) & shift_lt_rt;
ctrl1:=shift_by(1) & shift_lt_rt;
ctrl2:=shift_by(2) & shift_lt_rt;
if(rst_a = '1') then
d_out<="00000000";
elsif(clk'event and clk = '1') then

if (shift_by="000")then
  assert(false) report "Parallel load" severity warning;
elsif(shift_lt_rt='1')then
  assert(false) report "right shift" severity warning;
elsif(shift_lt_rt='0')then
  assert(false) report "left shift" severity warning;
 end if;

case ctrl0 is
  when "00"|"01" =>x:=d_in ;
  when "10" =>x:=d_in(6 downto 0) & d_in(7);
  when "11" =>x:=d_in(0) & d_in(7 downto 1);
  when others => null;
end case;
case ctrl1 is
  when "00"|"01" =>y:=x;
  when "10" =>y:=x(5 downto 0) & x(7 downto 6);
  when "11" =>y:=x(1 downto 0) & x(7 downto 2);
  when others => null;
end case;
case ctrl2 is
  when "00"|"01" =>d_out<=y ;
  when "10"|"11" =>d_out<= y(3 downto 0) & y(7 downto 4);
  when others => null;
end case;
end if;
  end process p1;
end beh;

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Barrel shifter with multi cycle vhdl code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity barrel_shifter_multi is
 
  port (
    d_in        : in  bit_vector(7 downto 0);   -- input vector
    d_out       : out bit_vector(7 downto 0);   -- shifted output
    shift_lt_rt : in  bit;                      -- 0=>left_operation 1=>right_operation
    shift_by    : in  bit_vector(2 downto 0);   -- 000=> parallel load other=>shift amount
    clk         : in  bit;                      -- clock signal
    rst_a       : in  bit);                     -- reset signal

end barrel_shifter_multi;

architecture beh of barrel_shifter_multi is
signal x,y,z : bit_vector(7 downto 0);
signal tmp,tmp2,tmp3 : bit_vector(7 downto 0);
signal ctrl0,ctrl1,ctrl2 : bit_vector(1 downto 0);
begin  -- beh

--ctrl0<=shift_by(0) & shift_lt_rt;
--ctrl1<=shift_by(1) & shift_lt_rt;
--ctrl2<=shift_by(2) & shift_lt_rt;

p1: process (clk, rst_a)
begin  -- process p1
  if rst_a = '1' then                   -- asynchronous reset (active high)
    tmp<="00000000";
  elsif clk'event and clk = '1' then    -- rising clock edge
    tmp<=d_in;
    ctrl0<=shift_by(0) & shift_lt_rt;
  end if;
end process p1;


s1: process (ctrl0,tmp,clk)
begin  -- process p2
case ctrl0 is
  when "00"|"01" =>x<=tmp ;
  when "10" =>x<=tmp(6 downto 0) & tmp(7);
  when "11" =>x<=tmp(0) & tmp(7 downto 1);
  when others => null;
end case;
end process s1;

p2: process (clk, rst_a)
begin  -- process p1
  if rst_a = '1' then                   -- asynchronous reset (active high)
    tmp2<="00000000";
  elsif clk'event and clk = '1' then    -- rising clock edge
    tmp2<=x;
    ctrl1<=shift_by(1) & shift_lt_rt;
  end if;
end process p2;

s2: process (ctrl1,tmp2,clk)
begin  -- process s2
  case ctrl1 is
  when "00"|"01" =>y<=tmp2;
  when "10" =>y<=tmp2(5 downto 0) & tmp2(7 downto 6);
  when "11" =>y<=tmp2(1 downto 0) & tmp2(7 downto 2);
  when others => null;
end case;
end process s2;

p3: process (clk, rst_a)
begin  -- process p1
  if rst_a = '1' then                   -- asynchronous reset (active high)
    tmp3<="00000000";
  elsif clk'event and clk = '1' then    -- rising clock edge
    tmp3<=y;
    ctrl2<=shift_by(2) & shift_lt_rt;
  end if;
end process p3;

s4: process (ctrl2,tmp3,clk)
begin  -- process s4
  case ctrl2 is
  when "00"|"01" =>z<=tmp3 ;
  when "10"|"11" =>z<= tmp3(3 downto 0) & tmp3(7 downto 4);
  when others => null;
end case;

end process s4;

p4: process (clk, rst_a)
begin  -- process p1
  if rst_a = '1' then                   -- asynchronous reset (active high)
    d_out<="00000000";
  elsif clk'event and clk = '1' then    -- rising clock edge
    d_out<=z;
  end if;
end process p4;
end beh;

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Barrel shifter with rotate left and write vhdl code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity barrel_shifter5 is
 
  port (
    rst_a       : in  std_logic;                     -- asynchronous reset input
    shift_lt : in  bit ;                                  -- shift by left
    shift_rt     : in  bit ;                                  -- shift by right
    d_in        : in  bit_vector(7 downto 0);        -- parallel data input
    clk         : in  bit;                           -- clock input
    d_out       : out bit_vector(7 downto 0);        -- barrel shifted output
    shift_by    : in  bit_vector(2 downto 0));       -- how much it should be shifted

end barrel_shifter5;

architecture beh of barrel_shifter5 is

--left shifting function
  function shift_lft (constant d :bit_vector(7 downto 0); signal shift1 :bit_vector(2 downto 0))
    return bit_vector is
    begin
       case shift1 is
       when "000" => return d;        --without shifting
       when "001" => return d rol 1;  --shift left by 1
       when "010" => return d rol 2;  --shift left by 2
       when "011" => return d rol 3;  --shift left by 3
       when "100" => return d rol 4;  --shift left by 4
       when "101" => return d rol 5;  --shift left by 5
       when "110" => return d rol 6;  --shift left by 6
       when "111" => return d rol 7;  --shift left by 7
       end case;
    return d;
   end shift_lft;

--right shifting function
   function shift_rgt (constant d :bit_vector(7 downto 0); signal shift1 :bit_vector(2 downto 0))
    return bit_vector is
    begin
       case shift1 is
       when "000" => return d;        --without shifting
       when "001" => return d ror 1;  --shift right by 1
       when "010" => return d ror 2;  --shift right by 2
       when "011" => return d ror 3;  --shift right by 3
       when "100" => return d ror 4;  --shift right by 4
       when "101" => return d ror 5;  --shift right by 5
       when "110" => return d ror 6;  --shift right by 6
       when "111" => return d ror 7;  --shift right by 7
       end case;
    return d;
   end shift_rgt;

                                 
begin  -- beh

shifter: process (clk,rst_a,shift_by,d_in,shift_lt,shift_rt)
variable tmp : bit_vector(7 downto 0);
begin  -- process shifter
 if rst_a = '1' then
    d_out<= "00000000";
    tmp:=d_in;
  elsif clk'event and clk='1' then
  if shift_lt=shift_rt then      -- parallel load
    assert(false) report "parallel load" severity warning;
      tmp:=d_in;
  elsif shift_lt>shift_rt then   -- shift left
    assert(false) report "left operation" severity warning;
      tmp:=shift_lft(tmp,shift_by);
   elsif shift_lt<shift_rt then  -- shift right
    assert(false) report "right operation" severity warning;
      tmp:=shift_rgt(tmp,shift_by);
   end if; 
d_out<=tmp;
end if;
end process shifter;
end beh;

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Parity generator with serial input and parallel output vhdl code

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity parity_gen is
 
  port (
    clk       : in  std_logic;
    rst_a     : in  std_logic;
    valid_in  : in  std_logic;
    d_in      : in  std_logic;          -- input serial data stream
    valid_out : out std_logic;
    parity    : out std_logic;
    data_o    : out std_logic_vector (7 downto 0));

end parity_gen;

architecture parity_gen_arch of parity_gen is

  component d_ff is
 
  port (
     rst  : in  std_logic;               -- asynchronous reset
     clk  : in  std_logic;               -- clock
     en   : in  std_logic;               -- control signal 
     d_in : in  std_logic;               -- input data
     q    : out std_logic                -- output data
    );           

  end component;
 
  function parity_gen_func (par : in std_logic_vector (7 downto 0)) return std_logic is
  begin
  return par(0)xor par(1)xor par(2)xor par(3)xor par(4)xor par(5)xor par(6)xor par(7);
  end parity_gen_func;

  signal count : std_logic_vector (2 downto 0) := "000";
  signal temp : std_logic_vector (7 downto 0);

begin  -- parity_gen_arch

   d_ff1: d_ff port map (rst_a, clk, valid_in, d_in, temp(0));
   d_ff2: d_ff port map (rst_a, clk, valid_in, temp(0), temp(1));
   d_ff3: d_ff port map (rst_a, clk, valid_in, temp(1), temp(2));
   d_ff4: d_ff port map (rst_a, clk, valid_in, temp(2), temp(3));
   d_ff5: d_ff port map (rst_a, clk, valid_in, temp(3), temp(4));
   d_ff6: d_ff port map (rst_a, clk, valid_in, temp(4), temp(5));
   d_ff7: d_ff port map (rst_a, clk, valid_in, temp(5), temp(6));
   d_ff8: d_ff port map (rst_a, clk, valid_in, temp(6), temp(7));
  
data_o<= temp;
parity <= parity_gen_func(temp);
  
p1:   process (clk, rst_a)
        begin       
    if rst_a = '1' then                 -- asynchronous reset
      valid_out <= '0';
     
    elsif clk'event and clk ='1' then
    if valid_in = '1' then
        count<= count + '1';   
    end if; 
    if count = "111" then
        valid_out <= '1';
    else
        valid_out <= '0';
    end if;
    end if;
  end process p1;
 
end parity_gen_arch;

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synchronous up down counter vhdl code and test bench

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity up_down_counter is
 
  port(clk, rst_a, mode : in std_logic;  --mode=1 up counting, mode=0 down counting
        q : out std_logic_vector(3 downto 0));

end up_down_counter;

architecture archi of up_down_counter is
  signal tmp: std_logic_vector(3 downto 0);
  begin 
    process (clk, rst_a)
      begin
        if (rst_a='1') then
          tmp <= "0000";
        elsif (clk'event and clk='1') then
          if (mode='1') then
            tmp <= tmp + 1;
          else
            tmp <= tmp - 1;
          end if;
        end if;
    end process;
    q <= tmp;
end archi;


Test Bench

 library ieee;
use ieee.std_logic_1164.all;

entity up_down_counter_tst is
 
end up_down_counter_tst;

architecture beh of up_down_counter_tst is
component up_down_counter
  port(clk, rst_a,mode : in std_logic;
      q : out std_logic_vector(3 downto 0));
end component;
signal clk_s,rst_a_s,mode_s : std_logic;
signal q_s : std_logic_vector(3 downto 0);
begin  -- beh

  u1 : up_down_counter port map (
    clk   => clk_s,
    rst_a => rst_a_s,
    mode  => mode_s,
    q     => q_s);

  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 55 ns;
    clk_s <= '0';
    wait for 55 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '0';
   wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;
    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;
  end process tst;
  end beh;

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up counter with preload vhdl code and test bench

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity up_counter_sync_preload is
 
  port(clk, rst_a,load : in std_logic;
       ip: in std_logic_vector(3 downto 0);
        q : out std_logic_vector(3 downto 0));

end up_counter_sync_preload;

architecture archi of up_counter_sync_preload is
  signal tmp: std_logic_vector(3 downto 0);
  begin 
    process (clk, rst_a)
      begin
        if (rst_a='1') then
          tmp <= "0000";
       elsif (clk'event and clk='1') then
          if (load='1') then
            tmp <= ip;
           
            assert (not(tmp - tmp'last_value = "0001"))
            report "counter difer by 1"
            severity warning;
         
          else
          tmp <= tmp + '1';
          end if;

      end if;

    end process;
    q <= tmp;

end archi;

--------------------------------
Test Bench
--------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity up_counter_sync_preload_tst is
 
end up_counter_sync_preload_tst;

architecture beh of up_counter_sync_preload_tst is
component up_counter_sync_preload
  port(clk, rst_a,load : in std_logic;
       ip: in std_logic_vector(3 downto 0);
        q : out std_logic_vector(3 downto 0));
end component;
signal clk_s,rst_a_s,load_s : std_logic;
signal ip_s,q_s : std_logic_vector(3 downto 0);
begin  -- beh

  u1 : up_counter_sync_preload port map (
    clk   => clk_s,
    rst_a => rst_a_s,
    load  => load_s,
    ip    => ip_s,
    q     => q_s);

  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 55 ns;
    clk_s <= '0';
    wait for 55 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;
    rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
        rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
        rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
        rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
        rst_a_s <= '0';
    load_s <= '1';
    ip_s <= "0101";
    wait for 100 ns;
        rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
  end process tst;
  end beh;

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d flipflop with setup/hold violation, reset recovery, clock width violation and output transition vhdl code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

 
  entity d_flipflop is
   
    generic (
          constant t_setup       : time := 5 ns;      -- setup time
          constant t_hold        : time := 5 ns;      -- hold time
          constant clk_width     : time := 54 ns;     -- clock width
          constant trans_time    : time := 3 ns;      -- output transition delay
          constant rst_reco_time : time := 3 ns       -- reset recovery time
    );
      port (
          data    :in  std_logic;  -- Data input
          clk     :in  std_logic;  -- Clock input
          reset_a :in  std_logic;  -- Reset input
          q       :out std_logic;  -- Q output
          load    :in  std_logic   -- load the input
      );
  end entity;
 
  architecture beh of d_flipflop is

    signal tmp : std_logic;
   
  begin

    p1:  process (clk,reset_a,load)
           begin
          
          if (reset_a = '1') then
              tmp <= '0' after 3 ns;
          elsif(rising_edge(clk)) then
              if(load = '1') then
              tmp <= '1'after 3 ns;
              else
                tmp<= data after 3 ns;
                end if;           
          end if;
        
       end process p1;

       chk_st: process (clk)
          begin  -- process chk_st
            if(clk'event and clk='1')then
              assert (data'stable(t_setup)) report "setup violation" severity error;
            end if;
          end process chk_st;

       chk_ht: process (clk'delayed(t_hold))
          begin  -- process chk_ht
            if(clk'delayed(t_hold)'event and clk'delayed(t_hold) = '1') then
              assert (data'last_event >= t_hold) report "hold time violation" severity error;
            end if;
          end process chk_ht;
         

       chk_wd: process (clk)
          variable last_time : time := 0 ns;
          begin  -- process chk_st
            assert (now-last_time > clk_width)
              report "clock width violation"
              severity warning;
            last_time := now;        
       end process chk_wd;
      
      
      chk_rst: process (clk,reset_a)
      begin  -- process chk_rst
        if(clk'event and clk='1')then
          assert (reset_a'stable(rst_reco_time)) report "reset recovery violation" severity warning;
        end if;
      end process chk_rst;
         
       chk: process
       begin  -- process chk
              if(clk'event and clk='1')then
                 wait for trans_time;
                  if(tmp'event and tmp='0') then
                    assert (not(clk'last_event-tmp'last_event=trans_time))
                    report "output dealy for high to low transition violation"
                    severity warning;
                 elsif(tmp'event and tmp='1') then
                    assert (not(clk'last_event-tmp'last_event=trans_time))
                    report "output dealy for low to high transition violation"
                    severity warning;
                  end if;
                end if;
                wait on clk,tmp;
              end process chk;
       q<=tmp;    

end architecture;

Test bench
--------------------------

library ieee;
use ieee.std_logic_1164.all;

entity d_flipflop_tst is
 
end d_flipflop_tst;

architecture beh of d_flipflop_tst is
component d_flipflop
  port (
    data, load, reset_a, clk: in  std_logic;   -- inputs
    q                             : out std_logic);  -- output
end component;
  signal data_s,load_s,reset_a_s,clk_s : std_logic := '0';
  signal q_s : std_logic;
begin  -- beh

  u1 : d_flipflop port map (
    data    => data_s,
    load    => load_s,
    reset_a => reset_a_s,
    clk     => clk_s,
    q       => q_s);

  tst_p: process
  begin  -- process tst_p
    clk_s <= '1';
    wait for 55 ns;
    clk_s <= '0';
    wait for 55 ns;
  end process tst_p;

 dff: process
 begin  -- process dff
   reset_a_s <= '1';
   load_s <= '1';
   data_s <= '0';
   wait for 109 ns;
   reset_a_s <= '0';
   load_s <= '1';
   data_s <= '1';
   wait for 112 ns;
   reset_a_s <= '0';
   load_s <= '0';
   data_s <= '0';
   wait for 100 ns;
   reset_a_s <= '0';
   load_s <= '0';
   data_s <= '1';
   wait for 100 ns;
  
 end process dff;
end beh;

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d flipflop with asynchronous reset enable and load vhdl code and test bench

library ieee;
use ieee.std_logic_1164.all;
 
  entity dff_async_reset is
      port (
          data    :in  std_logic;  -- Data input
          clk     :in  std_logic;  -- Clock input
          reset_a :in  std_logic;  -- Reset input
          q       :out std_logic;  -- Q output
          enb     :in  std_logic;  -- enable pin
          load    :in  std_logic   -- load the input
      );
  end entity;
 
  architecture beh of dff_async_reset is
 
  begin
      process (clk,reset_a,enb,load)
           begin
          
          if (reset_a = '1') then
              q <= '0';
          elsif(rising_edge(clk) and enb ='1') then
              if(load = '1') then
              q <= '1';
              else
                q<= data;
                end if;           
          end if;
    end process;
end architecture;



test bench
---------------------

library ieee;
use ieee.std_logic_1164.all;

entity dff_async_reset_tst is
 
end dff_async_reset_tst;

architecture beh of dff_async_reset_tst is
component dff_async_reset
  port (
    data, load, reset_a, clk, enb : in  std_logic;   -- inputs
    q                             : out std_logic);  -- output
end component;
  signal data_s,load_s,reset_a_s,clk_s,enb_s : std_logic := '0';
  signal q_s : std_logic;
begin  -- beh

  u1 : dff_async_reset port map (
    data    => data_s,
    load    => load_s,
    reset_a => reset_a_s,
    clk     => clk_s,
    enb     => enb_s,
    q       => q_s);

  tst_p: process
  begin  -- process tst_p
    clk_s <= '1';
    wait for 55 ns;
    clk_s <= '0';
    wait for 55 ns;
  end process tst_p;

 dff: process
 begin  -- process dff
   reset_a_s <= '1';
   enb_s <= '1';
   load_s <= '1';
   data_s <= '0';
   wait for 100 ns;
      reset_a_s <= '0';
   enb_s <= '1';
   load_s <= '1';
   data_s <= '0';
   wait for 100 ns;
      reset_a_s <= '0';
   enb_s <= '1';
   load_s <= '0';
   data_s <= '1';
   wait for 100 ns;
      reset_a_s <= '0';
   enb_s <= '1';
   load_s <= '0';
   data_s <= '0';
   wait for 100 ns;
  
 end process dff;
end beh;

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4 bit adder/substractor using full adder

library ieee;
use ieee.std_logic_1164.all;

entity add_sub_4b_using_fa is
 
  port (
    a, b : in  std_logic_vector(3 downto 0);   -- input bits
    enb  : in  std_logic;               -- en=0=>addition  ,  en=1 =>subtract
    c    : inout std_logic_vector(3 downto 0);   -- carry
    sd    : out std_logic_vector(3 downto 0));  -- sum/diff

end add_sub_4b_using_fa;

architecture beh of add_sub_4b_using_fa is
component full_adder
    port (
    ip1 : in  std_logic;
    ip2 : in  std_logic;
    ip3 : in  std_logic;
    sum : out std_logic;
    ca  : out std_logic);
end component;

component my_xor
  port (
    ip1 : in  std_logic;
    ip2 : in  std_logic;
    op1 : out std_logic);
end component;

signal b_s: std_logic_vector(3 downto 0);

begin  -- beh

u1: my_xor port map (enb,b(0),b_s(0));
u2: my_xor port map (enb,b(1),b_s(1));
u3: my_xor port map (enb,b(2),b_s(2));
u4: my_xor port map (enb,b(3),b_s(3));
u5: full_adder port map (a(0),b_s(0),enb,sd(0),c(0));
u6: full_adder port map (a(1),b_s(1),c(0),sd(1),c(1));
u7: full_adder port map (a(2),b_s(2),c(1),sd(2),c(2));
u8: full_adder port map (a(3),b_s(3),c(2),sd(3),c(3));
 

end beh;

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4 bit magnitude comparator vhdl code

library ieee;
use ieee.std_logic_1164.all;

entity mag_comp_4b is
 
  port (
    a, b       : in  std_logic_vector(3 downto 0);       -- inputs
    ag, bg, eq : out std_logic);                         -- ag if a > b, bg if b > a, eq if a=b

end mag_comp_4b;

architecture beh of mag_comp_4b is
signal s : std_logic_vector(3 downto 0);         -- intermediate signal
begin  -- beh

s(0)<= a(0) xnor b(0);
s(1)<= a(1) xnor b(1);
s(2)<= a(2) xnor b(2);
s(3)<= a(3) xnor b(3);
eq<=s(3) and s(2) and s(1) and s(0);
ag<=(a(3) and (not b(3))) or (s(3) and a(2) and (not b(2)))or (s(3) and s(2) and a(1)and (not b(1))) or (s(3) and s(2) and s(1) and a(0) and (not b(0)));
bg<=(b(3) and (not a(3))) or (s(3) and b(2) and (not a(2)))or (s(3) and s(2) and b(1)and (not a(1))) or (s(3) and s(2) and s(1) and b(0) and (not a(0)));
end beh;

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