4x1 mux primitive example in verilog

///////////////////////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
primitive mux_4x1(muxed_out,sel_1,sel_0,data1,data2,data3,data4);

   output muxed_out;
   input  sel_1,sel_0;
   input  data1,data2,data3,data4;


   table

      //sel_1 sel_0 data1 data2 data3 data4

      0 0 1 ? ? ? :1;
      0 0 0 ? ? ? :0;
      0 1 ? 1 ? ? :1;
      0 1 ? 0 ? ? :0;
      1 0 ? ? 1 ? :1;
      1 0 ? ? 0 ? :0;
      1 1 ? ? ? 1 :1;
      1 1 ? ? ? 0 :0;
      ? ? 0 0 0 0 :0;
      ? ? 1 1 1 1 :1;

   endtable
endprimitive // mux_4x1
 

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D flip flop primitive in verilog example

//////////////////////////////////////////////////////////////////////////////
// Design Name : dflip flop primitive
// File Name   : d_flipflop.v
// Function    :
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
primitive d_flipflop(q,clear,clk,d);
   output q;
   reg q;
   input      d,clk,clear;
   initial q=1'b1;

   table

  //clear clk d q

     
     
      0  ?   ? : ? : 0;
      1 (01) 1 : ? : 1;
      1 (01) 0 : ? : 0;
      1 (0?) 0 : ? : 0;
      1 (0?) 1 : ? : 1;
      1 (10) ? : ? : -;
      ?  ? (??) : ? : -;
      (??)  ? ? : ? : -;

   endtable
endprimitive // d_flipflop

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Vending Machine in Verilog

 //////////////////////////////////////////////////////////////////////////////
// Design Name : Vending Machine
// File Name   : vending.v
// Function    : at 15 rupee  req op will come
// Author      : Sidharth
//Permission   : This code only for educational purpose only
//cintact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module vending(out,coin,clk,rst);
  

  output reg out;
   input [1:0] coin;
   input       clk,rst;

   reg [1:0]   state,next_state;

   parameter s0=2'd0,
           s5=2'd1,
           s10=2'd2,
           s15=2'd3;

   parameter x0=2'd0,
           x5=2'd1,
           x10=2'd2,
           x15=2'd3;

   always @ (posedge clk)
     begin
    if(rst)
      state=s0;
    else
      state=next_state;
     end

   always @ (state,coin)
     begin
    case(state)

      s0:begin
         if(coin==x5)
           begin
          next_state=s5;
          out=0;
           end
        
         else if(coin==x0)
           begin
          next_state=s0;
          out=0;
           end
        
         else if(coin==x10)
           begin
          next_state=s10;
          out=0;
           end
      end // case: s0

      s5:begin
         if(coin==x0)
           begin
          next_state=s5;
          out=0;
           end
         else if(coin==x5)
           begin
          next_state=x10;
          out=0;
           end
         else if(coin==x10)
           begin
          next_state=s15;
          out=0;
           end
      end // case: s5

      s10:begin
         if(coin==x0)
           begin
          next_state=s10;
          out=0;
           end
         else if(coin==x5)
           begin
          next_state=x15;
          out=0;
           end
         else if(coin==x10)
           begin
          next_state=s15;
          out=0;
           end
      end // case: s10

      s15:
        begin
           out=1;
           next_state=s0;
        end
        endcase
      end // always @ (state,coin)
endmodule // vending

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Simple arbiter example in verilog

 //////////////////////////////////////////////////////////////////////////////
// Design Name : Design a Priority resolver for four requests using least recently algorithm.
// File Name   : priority_resolver_new.v
// Function    : priority resolver
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//cintact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module arbiter(gnt3,gnt2,gnt1,gnt0,req3,req2,req1,req0,clk,rst);

   output reg gnt3,gnt2,gnt1,gnt0;
   input      req3,req2,req1,req0;
   input      clk,rst;

   parameter idle=3'b000;
   parameter GNT3=3'b001;
   parameter GNT2=3'b010;
   parameter GNT1=3'b011;
   parameter GNT0=3'b100;

   reg [2:0]  state,next_state;

   always @ (posedge clk)
     begin
    if(rst)
      state=idle;
    else
      state=next_state;
     end

   always @ (state,req3,req2,req1,req0)
     begin
    next_state=0;

    case (state)

      idle:begin

         if(req0)
           next_state=GNT0;
         else if(req1)
           next_state=GNT1;
         else if(req2)
           next_state=GNT2;
         else if(req3)
           next_state=GNT3;
         else
           next_state=idle;
      end // case: idle

      GNT0:begin

         if(req0)
           next_state=GNT0;
         else
           next_state=idle;
      end

      GNT1:begin
         if(req1)
           next_state=GNT1;
         else
           next_state=idle;
      end

      GNT2:begin
         if(req2)
           next_state=GNT2;
         else
           next_state=idle;
      end

      GNT3:begin
         if(req3)
           next_state=GNT3;
         else
           next_state=idle;
      end
    endcase // case (state)
     end // always @ (state,req3,req2,req1,req0)

always @ (state)
  begin
     if(state==idle)
       begin
      gnt3=0;
      gnt2=0;
      gnt1=0;
      gnt0=0;
       end
     else if(state==GNT0)
       begin
      gnt3=0;
      gnt2=0;
      gnt1=0;
      gnt0=1;
       end
     else if(state==GNT1)
       begin
      gnt3=0;
      gnt2=0;
      gnt1=1;
      gnt0=0;
       end
     else if(state==GNT2)
       begin
      gnt3=0;
      gnt2=1;
      gnt1=0;
      gnt0=0;
       end
     else if(state==GNT3)
       begin
      gnt3=1;
      gnt2=0;
      gnt1=0;
      gnt0=0;
       end
  end // always @ (state)
endmodule // arbiter


        
         
  
    

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Priority resolver with least recent algorithm in verilog

//////////////////////////////////////////////////////////////////////////////
// Design Name : Design a Priority resolver for four requests using least recently algorithm.
// File Name   : priority_resolver_new.v
// Function    : priority resolver
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//cintact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////

module priority_resolver_new (grant,req,clk,rst_a);
 
  //----------input output port declaration
  
   output  [3:0] grant;        //granted user
   input [3:0]      req;          //requesting user
   input      clk;          //clock
   input      rst_a;        //asynchronous reset



  //---------internal signal declaration
  reg [6:0] count [3:0];      //counter for priority resolving
  reg [3:0] temp;
  reg [3:0] tmp_grant;
  reg [2:0] j;
 
  assign grant = tmp_grant;
  always @(posedge clk, posedge rst_a)
  begin
    if (rst_a)
          begin
            count[0]=7'b0;
            count[1]=7'b0;
            count[2]=7'b0;
            count[3]=7'b0;
           
          end
   else if (grant[0])
        begin
                            count[0]=0;
                            count[1]=count[1]+1;
                            count[2]=count[2]+1;
                            count[3]=count[3]+1; 
         end
       else if (grant[1])
        begin
                            count[0]=count[0]+1;
                            count[1]=0;
                            count[2]=count[2]+1;
                            count[3]=count[3]+1; 
         end
         else if (grant[2])
        begin
                            count[0]=count[0]+1;
                            count[1]=count[1]+1;
                            count[2]=0;
                            count[3]=count[3]+1;
         end
         else if (grant[3])
        begin
                            count[0]=count[0]+1;
                            count[1]=count[1]+1;
                            count[2]=count[2]+1;
                            count[3]=0; 
         end
    end
       
  always @(posedge clk,posedge rst_a)
    begin
        if (rst_a)
          begin
            tmp_grant = 4'b0;
          end
       else if (count[0]==0&&count[1]==0&&count[2]==0&&count[3]==0)//intial contion priority req[0]>req[1]>req[3]>req[4]
              begin
                if (req[0])
                  begin
                  tmp_grant[0]=1'b1;
                  tmp_grant[3:1]=3'b0;
                  end
                else if (req[1])
                  begin
                  tmp_grant[0]=1'b0;
                  tmp_grant[1]=1'b1;
                  tmp_grant[2]=1'b0;
                  tmp_grant[3]=1'b0;
                  end
                else if (req[2])
                  begin
                  tmp_grant[0]=1'b0;
                  tmp_grant[1]=1'b0;
                  tmp_grant[2]=1'b1;
                  tmp_grant[3]=1'b0;
                  end
                else if (req[3])
                  begin
                  tmp_grant[0]=1'b0;
                  tmp_grant[1]=1'b0;
                  tmp_grant[2]=1'b0;
                  tmp_grant[3]=1'b1;
                  end
              end
            else                                                                                                                                     
                       if (!count[0]&&req[0])          //for req=0001
                        tmp_grant = 4'b0001;
                        else if (!count[1]&&req[1])    //for req=0010
                        tmp_grant = 4'b0010;
                        else if (!count[2]&&req[2])    //for req=0100
                        tmp_grant = 4'b0100;
                        else if (!count[3]&&req[3])    //for req=1000
                        tmp_grant = 4'b1000;
                        else
                          begin
                            tmp_grant = 4'b0;
                          if (req[0])
                              temp=count[0];
                          else if (req[1])
                            temp=count[1];
                           else if (req[2])
                           temp=count[2];
                            else if (req[3])
                             temp=count[3];
                            
                             for(j=3'b0;j<=3'b011;j=j+1) //for more than one req
                                begin
                                  
                                   if (req[j])
                                        if(temp<=count[j])
                                          begin
                                            tmp_grant=0;
                                          temp=count[j];
                                          tmp_grant[j]=1'b1;
                                          end
                                       else
                                          tmp_grant[j]=1'b0;
                                    else
                                         tmp_grant[j]=1'b0;   
                                end
                  end
          end
         endmodule  

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Synchronous FIFO with synchronous read and write with test bench in verilog

/////////////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module sync_fifo(data_out,full,empty,data_in,clk,rst_a,wr_en,rd_en);

   parameter data_width    = 4;
   parameter address_width = 4;
   parameter ram_depth     =16;


   output [data_width-1:0] data_out;
   output            full;
   output            empty;
   input [data_width-1:0]  data_in;
   input            clk;
   input            rst_a;
   input            wr_en;
   input            rd_en;


   reg [address_width-1:0]    wr_pointer;
   reg [address_width-1:0]    rd_pointer;
   reg [address_width :0]     status_count;
   reg [data_width-1:0]       data_out ;
   wire [data_width-1:0]      data_ram ;


  

   always @ (posedge clk,posedge rst_a)
     begin
    if(rst_a)
      wr_pointer = 0;
    else
      if(wr_en)
        wr_pointer = wr_pointer+1;
     end

   always @ (posedge clk,posedge rst_a)
     begin
    if(rst_a)
      rd_pointer = 0;
    else
      if(rd_en)
        rd_pointer = rd_pointer+1;
     end

   always @ (posedge clk,posedge rst_a)
     begin
    if(rst_a)
      data_out=0;
    else
      if(rd_en)
        data_out=data_ram;
     end

   always @ (posedge clk,posedge rst_a)
     begin
    if(rst_a)
      status_count = 0;
    else
      if(wr_en && !rd_en && (status_count != ram_depth))
        status_count = status_count + 1;
      else
        if(rd_en && !wr_en && (status_count != 0))
          status_count = status_count - 1;
     end // always @ (posedge clk,posedge rst_a)


   assign full = (status_count == (ram_depth-1));
   assign empty = (status_count == 0);
  
   memory_16x4 #(data_width,address_width,ram_depth) u1 (.address_1(wr_pointer),.address_2(rd_pointer),.data_1(data_in),.data_2(data_ram),.wr_en1(wr_en),.rd_en2(rd_en),.clk(clk));


endmodule // sync_fifo


---------------------------------------------------

memory_16x4
----------------------------------------------------
module memory_16x4(data_1,data_2,wr_en1,rd_en2,clk,address_1,address_2);

   parameter data_width    = 4;
   parameter address_width = 4;
   parameter ram_depth     =16;

  
   input     [data_width-1:0]      data_1;
   output     [data_width-1:0]      data_2;
   input     [address_width-1:0]   address_1;
   input     [address_width-1:0]   address_2;
   input                           wr_en1,clk,rd_en2;

  
   reg [address_width-1:0]     memory[0:ram_depth-1];
   reg [data_width-1:0]        data_2_out;
   wire [data_width-1:0]  data_2;
  

   always @(posedge clk)
     begin
    if (wr_en1)
      memory[address_1]=data_1;
     end

   always @(posedge clk)
     begin
    if (rd_en2)
      data_2_out=memory[address_2];
     end

   assign data_2=(rd_en2)?data_2_out:8'b0;

endmodule // memory_16x4
----------------------------------------------------------------

test bench
----------------------------------------------------------------

`timescale 1ns/1ps
module sync_fifo_tb;
reg [3:0]  data_in;
reg        clk,rst_a,wr_en,rd_en;
wire [3:0] data_out;
wire    full,empty;
  


sync_fifo u1 (.data_out(data_out),.full(full), .empty(empty), .wr_en(wr_en), .rd_en(rd_en), .clk(clk), .rst_a(rst_a), .data_in(data_in));

initial
begin
clk=1'b1;
forever #50 clk=~clk;
end

initial
begin
   rst_a=1'b1;
   data_in=4'b0000;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

   rst_a=1'b0;
   data_in=4'b0001;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

   rst_a=1'b0;
   data_in=4'b0010;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

   rst_a=1'b0;
   data_in=4'b0011;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

   rst_a=1'b0;
   data_in=4'b0100;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

   rst_a=1'b0;
   data_in=4'b0101;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

      rst_a=1'b0;
   data_in=4'b0110;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

      rst_a=1'b0;
   data_in=4'b0111;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;


   data_in=4'b1000;
   #100;


   data_in=4'b1001;
   #100;


   data_in=4'b1010;
   #100;


   data_in=4'b1011;
   #100;

   data_in=4'b1100;
   #100;

   data_in=4'b1101;
   #100;

   data_in=4'b1110;
   #100;

   data_in=4'b1111;
   #100;

   rd_en=1'b1;
   wr_en=1'b0;
   #1600;
  
   rst_a=1'b1;
   data_in=4'b0101;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

   rst_a=1'b0;
   data_in=4'b0101;
   wr_en=1'b1;
   rd_en=1'b0;
   #100;

   rst_a=1'b0;
   data_in=4'b0110;
   wr_en=1'b0;
   rd_en=1'b1;
   #400;

  
$stop;
end
endmodule

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16X4 MEMORY WITH BI DIRECTIONAL PORT IN VERILOG WITH TEST BENCH

/////////////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module memory_16x4_bi(data, clk, out_en, address, rd_en, wr_en );
   inout [0:3] data;
   input clk;
   input out_en;
   input rd_en, wr_en;
   input [0:3] address;
   reg [0:3] memory [0:15];
   reg [0:3] data_out;


   assign data = out_en ? data_out : 4'bZ;
  
   always@(posedge clk)
     begin
    if(rd_en)
      data_out = memory[address];
    else if (wr_en)
      memory[address] = data;
    else data_out = 4'bx;
   
     end
  
   

endmodule
-----------------------------------------------------------------

test bench
------------------------------------------------------------------

`timescale 1ns/1ps
module memory_16x4_bi_tst;
   wire [0:3] data;
   reg clk;
   reg out_en;
   reg rd_en, wr_en;
   reg [0:3] address;
   reg [0:3] data1;
  

   memory_16x4_bi u1 (.data(data), .clk(clk), .out_en(out_en),.address(address), .rd_en(rd_en), .wr_en(wr_en));

   assign data = !out_en ? data1 : 4'bZ;
   //assign data = data1;
initial
  begin
     clk=1'b1;
     forever #50 clk=~clk;  
  end
 
initial
begin

   out_en = 1'b0;
   wr_en = 1'b1;
   rd_en=1'b0;
   address= 4'b0000;
   data1= 4'b1111;
  
   #100;
  
   address=4'b0001;
   data1 = 4'b0110;
  
   #100;
  
   address=4'b0010;
   data1 = 4'b0111;
  
   #100;
  
   out_en = 1'b1;
   address= 4'b0001;
   wr_en = 1'b0;
   rd_en=1'b1;
  
   #100
   address=4'b0010;
  
   #100;
  
  
   out_en = 1'b0;
   wr_en = 1'b1;
   rd_en=1'b0;
   address= 4'b0011;
   data1= 4'b0011;
  

   #100;
   out_en = 1'b1;
   address= 4'b0010;
   wr_en = 1'b0;
   rd_en=1'b1;
   #100


     $stop;
   end

endmodule

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sequential multiplier in verilog

/////////////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module seq_multi_4b(op,ready_out,a,b,load,clk,rst_a);
output reg [7:0] op;
output reg ready_out;
input [3:0] a,b;
input load,clk,rst_a;
reg [7:0] tmp,tmp0,tmp1,tmp2,tmp3;
reg [3:0] tmp_a;
  
always @(posedge clk)
  begin
     if(load)
       tmp_a=a;
       tmp={4'b0000,b};
  end
  
  

always @(tmp_a,load,tmp)
//begin
//if(load)
begin
case (tmp_a[0])
        1'b0:tmp0=8'b0000_0000;
        1'b1:tmp0=tmp;
endcase
case (tmp_a[1])
        1'b0:tmp1=8'b0000_0000;
        1'b1:tmp1=tmp<<1;
endcase
case (tmp_a[2])
        1'b0:tmp2=8'b0000_0000;
        1'b1:tmp2=tmp<<2;
endcase
case (tmp_a[3])
        1'b0:tmp3=8'b0000_0000;
        1'b1:tmp3=tmp<<3;
endcase // case (tmp_a[3])
//end
end // always @ (tmp,tmp_a)


always @ (posedge clk,posedge rst_a)
begin
     if(rst_a)
       begin
      op=0;
      ready_out=0;
    end
     else
       if(load)
         begin
        op=tmp0+tmp1+tmp2+tmp3;
        ready_out=1'b1;
        end
end

endmodule               

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Universal shifter in verilog with test bench

/////////////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth(DVLSI 31)
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module uni_shift_8b(op,clk,rst_a, load,sh_ro_lt_rt,ip);
  output reg [7:0] op;
  input load;
  input [1:0] sh_ro_lt_rt;
  input [7:0] ip;
  input clk, rst_a;
 
  reg [7:0]temp;
 
 
 
  always @(posedge clk or posedge rst_a)
   begin
     if (rst_a)
      
       op = 0;
     
     else   
       case(load)
         1'b1:
          begin                            //Load Input
            temp = ip;
          //  op = temp;
          end
         1'b0:                             //Operation
          case (sh_ro_lt_rt)
            2'b00:  op = temp<<1;     //Left Shift
            2'b01:  op = temp>>1;     //Right Shift
            2'b10:  op = {temp[6:0],temp[7]}; //Rotate Left
            2'b11:  op = {temp[0], temp[7:1]};  //Rotate Right
                  
            default: $display("Invalid Shift Control Input");
          endcase
     
       
        
        default: $display("Invalid Load Control Input");
        endcase
  
    end
   
  endmodule
         
   -----------------------------------------------------------

test bench
----------------------------------------------------------------
`timescale 1ns/1ps

module uni_shift_8b_tst;
  reg [7:0] ip;
  reg [1:0] sh_ro_lt_rt;
  reg         load,rst_a,clk;
  wire [7:0] op;


   uni_shift_8b u1 (.op(op), .ip(ip), .sh_ro_lt_rt(sh_ro_lt_rt), .load(load) , .rst_a(rst_a) , .clk(clk));

initial
  begin
     clk=1'b1;
     forever #50 clk=~clk;  
  end
 
   initial
     begin
    ip = 8'b11001100;
    rst_a = 1'b1;
    load = 1'b1;
    sh_ro_lt_rt = 2'b00;
    #100;
   
    ip = 8'b10001100;
    rst_a = 1'b0;
    load = 1'b1;
    sh_ro_lt_rt = 2'b01;
    #100;
   
    ip = 8'b11001100;

    load = 1'b0;
    sh_ro_lt_rt = 2'b01;
    #100;
   
    ip = 8'b10101101;
   
    load = 1'b1;
    sh_ro_lt_rt = 2'b01;
    #100;
   
    ip = 8'b11001101;

    load = 1'b0;
    sh_ro_lt_rt = 2'b01;
    #100;

    ip = 8'b11101100;
    load = 1'b1;
    sh_ro_lt_rt = 2'b10;
    #100;

    ip = 8'b11110000;
    load = 1'b0;
    sh_ro_lt_rt = 2'b10;
    #100;

    ip = 8'b11001100;
    load = 1'b1;
    sh_ro_lt_rt = 2'b11;
    #100;

    ip = 8'b11001101;
    load = 1'b0;
    sh_ro_lt_rt = 2'b11;
    #100;
   
    ip = 8'b11001000;
    load = 1'b1;
    sh_ro_lt_rt = 2'b11;
    #100;
    $stop;
     end // initial begin
   endmodule
   
  

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ALU in verilog with test bench

/////////////////////////////////////////////////////////////////////////////////////
// Author      : Sidharth
//Permission   : This code only for educational purpose only
//contact      :sidharth.sankar77@gmail.com
//////////////////////////////////////////////////////////////////////////////
module alu (op,a,b,c_log_arith);

  output reg [3:0] op;     //output of alu
   input [3:0]        a,b;    //inputs to alu
   input [1:0] c_log_arith;//control signal for logical/arithmatic operation

   always @(*)

    begin
    case (c_log_arith)
      2'b00 : begin op = a + b; $display("Addition operation"); end
      2'b01 : begin op = a - b; $display("Subtraction operation"); end
      2'b10 : begin op = ~(a & b); $display("logical NAND operation"); end
      2'b11 : begin op = a ^ b; $display("Logical XOR operation"); end

      default:op = 4'bXXXX;
    endcase

    end


endmodule

----------------------------------------------

test bench
-----------------------------------------------
`timescale 1ns/1ps
module alu_tst;
  reg [3:0] a,b;
  reg [1:0] c_log_arith;
  wire [3:0] op;


   alu u1 (.op(op), .a(a), .b(b) , .c_log_arith(c_log_arith));


   initial
     begin
   
    a=4'b0011;
    b=4'b1101;
    c_log_arith=2'b00;
    #100;
   
    a=4'b1101;
    b=4'b1111;
    c_log_arith=2'b01;
    #100;
   
    a=4'b0011;
    b=4'b1100;
    c_log_arith=2'b10;
    #100;
   
    a=4'b1110;
    b=4'b0100;
    c_log_arith=2'b11;
    #100;

    a=4'b0111;
    b=4'b1001;
    c_log_arith=2'b00;
    #100;
   
    a=4'b1111;
    b=4'b1111;
    c_log_arith=2'b01;
    #100;
   
    a=4'b1011;
    b=4'b1101;
    c_log_arith=2'b10;
    #100;
   
    a=4'b1110;
    b=4'b0111;
    c_log_arith=2'b11;
    #100
    $stop;
     end
   endmodule
   
  

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4 bit full adder verilog code

module full_adder_4b(sum,cout,a,b,cin);
   output [3:0] sum;
   output     cout;
   input [3:0]     a,b;
   input     cin;

   full_adder f1 (sum[0], cout0, a[0], b[0], cin);
   full_adder f2 (sum[1], cout1, a[1], b[1], cout0);
   full_adder f3 (sum[2], cout2, a[2], b[2], cout1);
   full_adder f4 (sum[3], cout, a[3], b[3], cout2);

   endmodule

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D latch verilog code

module d_latch(q, q_bar, d_in, enb);

   output q,q_bar;
   input  d_in;
   input  enb;

   nand g1 (s, d_in, enb),
        g2 (r, d_bar, enb);
  
   not g3 (d_bar,d_in);
   nand g4 (q, s, q_bar);
   nand g5 (q_bar, r, q);

   endmodule
  

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4:16 decoder verilog code

module decoder_4x16 (d_out, d_in);
   output [15:0] d_out;
   input [3:0]      d_in;
   parameter tmp = 16'b0000_0000_0000_0001;
  


assign d_out = (d_in == 4'b0000) ? tmp   :
               (d_in == 4'b0001) ? tmp<<1:
               (d_in == 4'b0010) ? tmp<<2:
           (d_in == 4'b0011) ? tmp<<3:
           (d_in == 4'b0100) ? tmp<<4:
           (d_in == 4'b0101) ? tmp<<5:
           (d_in == 4'b0110) ? tmp<<6:
           (d_in == 4'b0111) ? tmp<<7:
           (d_in == 4'b1000) ? tmp<<8:
           (d_in == 4'b1001) ? tmp<<9:
           (d_in == 4'b1010) ? tmp<<10:
           (d_in == 4'b1011) ? tmp<<11:
           (d_in == 4'b1100) ? tmp<<12:
           (d_in == 4'b1101) ? tmp<<13:
           (d_in == 4'b1110) ? tmp<<14:
           (d_in == 4'b1111) ? tmp<<15: 16'bxxxx_xxxx_xxxx_xxxx;
            
              
             endmodule

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Priority encoder verilog code

module prio_enco_8x3(d_out, d_in);

   output [2:0] d_out;
   input [7:0] d_in ;


assign d_out = (d_in[7] ==1'b1 ) ? 3'b111:
               (d_in[6] ==1'b1 ) ? 3'b110:
               (d_in[5] ==1'b1 ) ? 3'b101:
                 (d_in[4] ==1'b1) ? 3'b100:
                 (d_in[3] ==1'b1) ? 3'b011:
                 (d_in[2] ==1'b1) ? 3'b010:
                 (d_in[1] ==1'b1) ? 3'b001: 3'b000;

   endmodule

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Parity generator structural vhdl code

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity parity_gen is
 
  port (
    clk       : in  std_logic;
    rst_a     : in  std_logic;
    valid_in  : in  std_logic;
    d_in      : in  std_logic;          -- input serial data stream
    valid_out : out std_logic;
    parity    : out std_logic;
    data_o    : out std_logic_vector (7 downto 0));

end parity_gen;

architecture parity_gen_arch of parity_gen is

  component d_ff is
 
  port (
     rst  : in  std_logic;               -- asynchronous reset
     clk  : in  std_logic;               -- clock
     en   : in  std_logic;               -- control signal 
     d_in : in  std_logic;               -- input data
     q    : out std_logic                -- output data
    );           

  end component;
 
  function parity_gen_func (par : in std_logic_vector (7 downto 0)) return std_logic is
  begin
  return par(0)xor par(1)xor par(2)xor par(3)xor par(4)xor par(5)xor par(6)xor par(7);
  end parity_gen_func;

  signal count : std_logic_vector (2 downto 0) := "000";
  signal temp : std_logic_vector (7 downto 0);

begin  -- parity_gen_arch

   d_ff1: d_ff port map (rst_a, clk, valid_in, d_in, temp(0));
   d_ff2: d_ff port map (rst_a, clk, valid_in, temp(0), temp(1));
   d_ff3: d_ff port map (rst_a, clk, valid_in, temp(1), temp(2));
   d_ff4: d_ff port map (rst_a, clk, valid_in, temp(2), temp(3));
   d_ff5: d_ff port map (rst_a, clk, valid_in, temp(3), temp(4));
   d_ff6: d_ff port map (rst_a, clk, valid_in, temp(4), temp(5));
   d_ff7: d_ff port map (rst_a, clk, valid_in, temp(5), temp(6));
   d_ff8: d_ff port map (rst_a, clk, valid_in, temp(6), temp(7));
  
data_o<= temp;
parity <= parity_gen_func(temp);
  
p1:   process (clk, rst_a)
        begin       
    if rst_a = '1' then                 -- asynchronous reset
      valid_out <= '0';
     
    elsif clk'event and clk ='1' then
    if valid_in = '1' then
        count<= count + '1';   
    end if; 
    if count = "111" then
        valid_out <= '1';
    else
        valid_out <= '0';
    end if;
    end if;
  end process p1;
 
end parity_gen_arch;

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