Run multiple testcases in System Verilog in Questasim

Let there are two test cases. testcase1 and testcase2 1-First complie them using the command(for questasim)  vlog  top.sv test_case1.sv vlog   top.sv   test_case2.sv 2-To run them use command as given below  vsim top +test_case1 vsim  top  +test_case2...

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System Verilog Inheritance example

/*-----------------------------------BASE CLASS----------------*/ class base;    logic [7:0] data;    task increament(logic[7:0] temp);      data=temp+1;    endtask // increament    task random();       this.data=$random;    endtask // random endclass // base /*-----------------------------------DERIVED CLASS----------------*/ class derived extends base;    logic[7:0] packet[];    int size;    function new(int size);    ...

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