Priority resolver with least recent algorithm in verilog

//////////////////////////////////////////////////////////////////////////////// Design Name : Design a Priority resolver for four requests using least recently algorithm.// File Name   : priority_resolver_new.v// Function    : priority resolver// Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//cintact      :sidharth.sankar77@gmail.com//////////////////////////////////////////////////////////////////////////////module...

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Synchronous FIFO with synchronous read and write with test bench in verilog

///////////////////////////////////////////////////////////////////////////////////// // Author      : Sidharth(DVLSI 31) //Permission   : This code only for educational purpose only //contact      :sidharth.sankar77@gmail.com ////////////////////////////////////////////////////////////////////////////// module sync_fifo(data_out,full,empty,data_in,clk,rst_a,wr_en,rd_en);    parameter data_width    = 4;    parameter address_width = 4;   ...

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Sequential multiplier using booth algorithm in verilog with test bench

//----------------------------------------------------- // Design Name : Design and verify a sequential multiplier using Booths algorithm // File Name   : booth_seq_multi.v // Function    : Signed multiplication // Author      :  Sidharth(DVLSI 31) //----------------------------------------------------- module booth_seq_multi(op,clk,rst_a,load,a,b);    //parameter declaration-----------------------------    parameter ip1_data_width = 4;    parameter ip2_data_width...

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16X4 MEMORY WITH BI DIRECTIONAL PORT IN VERILOG WITH TEST BENCH

///////////////////////////////////////////////////////////////////////////////////// // Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//contact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// module memory_16x4_bi(data, clk, out_en, address, rd_en, wr_en );    inout [0:3] data;    input clk;    input out_en;    input rd_en, wr_en;   ...

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sequential multiplier in verilog

///////////////////////////////////////////////////////////////////////////////////// // Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//contact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// module seq_multi_4b(op,ready_out,a,b,load,clk,rst_a); output reg [7:0] op; output reg ready_out; input [3:0] a,b; input load,clk,rst_a; reg [7:0] tmp,tmp0,tmp1,tmp2,tmp3; reg [3:0] tmp_a;   ...

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Universal shifter in verilog with test bench

///////////////////////////////////////////////////////////////////////////////////// // Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//contact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// module uni_shift_8b(op,clk,rst_a, load,sh_ro_lt_rt,ip);   output reg [7:0] op;   input load;   input [1:0] sh_ro_lt_rt;   input [7:0] ip;   input clk, rst_a;  ...

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ALU in verilog with test bench

///////////////////////////////////////////////////////////////////////////////////// // Author      : Sidharth //Permission   : This code only for educational purpose only //contact      :sidharth.sankar77@gmail.com ////////////////////////////////////////////////////////////////////////////// module alu (op,a,b,c_log_arith);   output reg [3:0] op;     //output of alu    input [3:0]        a,b;    //inputs...

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