Finite state machine -pattern checker in vhdl

When a certain serial binary communication channel is operating correctly, all blocks of 0's are of even length and all blocks of 1's are of odd length. The machine should produce and output pulse z = 1 whenever discrepancy from the above pattern is detected. Example: X : 0 0 1 0 0 0 1 1 1 0 1 1 0 0… Z : 0 0 0 0 0 0 1 0 0 0 1 0 1 0… library ieee; use ieee.std_logic_1164.all; entity fsm_prob3 is     port (     clk                : in ...

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User defined package in vhdl example

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; package combo_logic is   function mux2x1 (d1,d2,sel : std_logic) return std_logic;   function parity_chk (signal d_in : std_logic_vector) return std_logic;   function left_shift (signal d_in : std_logic_vector; signal shift_by : integer)  return bit_vector;   function right_shift (signal d_in : std_logic_vector; signal shift_by : integer) return bit_vector;    end combo_logic; package body combo_logic is -------------------------------------------------------------------------------- --function...

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4 bit full adder verilog code

module full_adder_4b(sum,cout,a,b,cin);    output [3:0] sum;    output     cout;    input [3:0]     a,b;    input     cin;    full_adder f1 (sum[0], cout0, a[0], b[0], cin);    full_adder f2 (sum[1], cout1, a[1], b[1], cout0);    full_adder f3 (sum[2], cout2, a[2], b[2], cout1);    full_adder f4 (sum[3], cout, a[3], b[3], cout2);    endmodu...

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D latch verilog code

module d_latch(q, q_bar, d_in, enb);    output q,q_bar;    input  d_in;    input  enb;    nand g1 (s, d_in, enb),         g2 (r, d_bar, enb);       not g3 (d_bar,d_in);    nand g4 (q, s, q_bar);    nand g5 (q_bar, r, q);    endmodule   ...

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4:16 decoder verilog code

module decoder_4x16 (d_out, d_in);    output [15:0] d_out;    input [3:0]      d_in;    parameter tmp = 16'b0000_0000_0000_0001;    assign d_out = (d_in == 4'b0000) ? tmp   :                (d_in == 4'b0001) ? tmp<<1:                (d_in == 4'b0010) ? tmp<<2:            (d_in ==...

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Priority encoder verilog code

module prio_enco_8x3(d_out, d_in);    output [2:0] d_out;    input [7:0] d_in ; assign d_out = (d_in[7] ==1'b1 ) ? 3'b111:                (d_in[6] ==1'b1 ) ? 3'b110:                (d_in[5] ==1'b1 ) ? 3'b101:                  (d_in[4] ==1'b1) ? 3'b100:                 ...

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Parity generator structural vhdl code

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity parity_gen is     port (     clk       : in  std_logic;     rst_a     : in  std_logic;     valid_in  : in  std_logic;     d_in      : in  std_logic;          -- input serial data stream     valid_out : out...

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Barrel shifter with multi cycle and textio vhdl code

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity barrel_shifter_multi is     port (     d_in          : in bit_vector (7 downto 0);     clk, rst_a    : in bit;     shift_lt_rt   : in bit;                     --0=>left shift , 1=> right shift    ...

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Vhdl code for barrel shifter with single cycle

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity barrel_shifter is     port (     d_in        : in  bit_vector(7 downto 0);   -- input vector     d_out       : out bit_vector(7 downto 0);   -- shifted output     shift_lt_rt : in  bit;                     ...

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Barrel shifter with multi cycle vhdl code

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity barrel_shifter_multi is     port (     d_in        : in  bit_vector(7 downto 0);   -- input vector     d_out       : out bit_vector(7 downto 0);   -- shifted output     shift_lt_rt : in  bit;                     ...

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Barrel shifter with rotate left and write vhdl code

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity barrel_shifter5 is     port (     rst_a       : in  std_logic;                     -- asynchronous reset input     shift_lt : in  bit ;                       ...

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Parity generator with serial input and parallel output vhdl code

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity parity_gen is     port (     clk       : in  std_logic;     rst_a     : in  std_logic;     valid_in  : in  std_logic;     d_in      : in  std_logic;          -- input serial data stream     valid_out...

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