Run multiple testcases in System Verilog in Questasim

Let there are two test cases. testcase1 and testcase2 1-First complie them using the command(for questasim)  vlog  top.sv test_case1.sv vlog   top.sv   test_case2.sv 2-To run them use command as given below  vsim top +test_case1 vsim  top  +test_case2...

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System Verilog Inheritance example

/*-----------------------------------BASE CLASS----------------*/ class base;    logic [7:0] data;    task increament(logic[7:0] temp);      data=temp+1;    endtask // increament    task random();       this.data=$random;    endtask // random endclass // base /*-----------------------------------DERIVED CLASS----------------*/ class derived extends base;    logic[7:0] packet[];    int size;    function new(int size);    ...

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Single Port RAM in VHDL using generate statement

//////////////////////////////////////////////////////////////////////////////// Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//contact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// library ieee;use ieee.std_logic_1164.all;entity memory_sp is    port (    clk      : in  std_logic;    address  : in ...

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4x1 mux primitive example in verilog

/////////////////////////////////////////////////////////////////////////////////////////////// // Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//contact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// primitive mux_4x1(muxed_out,sel_1,sel_0,data1,data2,data3,data4);   output muxed_out;   input  sel_1,sel_0;   input  data1,data2,data3,data4;  ...

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D flip flop primitive in verilog example

//////////////////////////////////////////////////////////////////////////////// Design Name : dflip flop primitive// File Name   : d_flipflop.v// Function    : // Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//contact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// primitive d_flipflop(q,clear,clk,d);   output q;   reg q;  ...

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Vending Machine in Verilog

 //////////////////////////////////////////////////////////////////////////////// Design Name : Vending Machine// File Name   : vending.v// Function    : at 15 rupee  req op will come // Author      : Sidharth//Permission   : This code only for educational purpose only//cintact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// module vending(out,coin,clk,rst);     output reg...

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Simple arbiter example in verilog

 //////////////////////////////////////////////////////////////////////////////// Design Name : Design a Priority resolver for four requests using least recently algorithm.// File Name   : priority_resolver_new.v// Function    : priority resolver// Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//cintact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// module...

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Priority resolver with least recent algorithm in verilog

//////////////////////////////////////////////////////////////////////////////// Design Name : Design a Priority resolver for four requests using least recently algorithm.// File Name   : priority_resolver_new.v// Function    : priority resolver// Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//cintact      :sidharth.sankar77@gmail.com//////////////////////////////////////////////////////////////////////////////module...

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Synchronous FIFO with synchronous read and write with test bench in verilog

///////////////////////////////////////////////////////////////////////////////////// // Author      : Sidharth(DVLSI 31) //Permission   : This code only for educational purpose only //contact      :sidharth.sankar77@gmail.com ////////////////////////////////////////////////////////////////////////////// module sync_fifo(data_out,full,empty,data_in,clk,rst_a,wr_en,rd_en);    parameter data_width    = 4;    parameter address_width = 4;   ...

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Sequential multiplier using booth algorithm in verilog with test bench

//----------------------------------------------------- // Design Name : Design and verify a sequential multiplier using Booths algorithm // File Name   : booth_seq_multi.v // Function    : Signed multiplication // Author      :  Sidharth(DVLSI 31) //----------------------------------------------------- module booth_seq_multi(op,clk,rst_a,load,a,b);    //parameter declaration-----------------------------    parameter ip1_data_width = 4;    parameter ip2_data_width...

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16X4 MEMORY WITH BI DIRECTIONAL PORT IN VERILOG WITH TEST BENCH

///////////////////////////////////////////////////////////////////////////////////// // Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//contact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// module memory_16x4_bi(data, clk, out_en, address, rd_en, wr_en );    inout [0:3] data;    input clk;    input out_en;    input rd_en, wr_en;   ...

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sequential multiplier in verilog

///////////////////////////////////////////////////////////////////////////////////// // Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//contact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// module seq_multi_4b(op,ready_out,a,b,load,clk,rst_a); output reg [7:0] op; output reg ready_out; input [3:0] a,b; input load,clk,rst_a; reg [7:0] tmp,tmp0,tmp1,tmp2,tmp3; reg [3:0] tmp_a;   ...

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Universal shifter in verilog with test bench

///////////////////////////////////////////////////////////////////////////////////// // Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//contact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// module uni_shift_8b(op,clk,rst_a, load,sh_ro_lt_rt,ip);   output reg [7:0] op;   input load;   input [1:0] sh_ro_lt_rt;   input [7:0] ip;   input clk, rst_a;  ...

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ALU in verilog with test bench

///////////////////////////////////////////////////////////////////////////////////// // Author      : Sidharth //Permission   : This code only for educational purpose only //contact      :sidharth.sankar77@gmail.com ////////////////////////////////////////////////////////////////////////////// module alu (op,a,b,c_log_arith);   output reg [3:0] op;     //output of alu    input [3:0]        a,b;    //inputs...

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Finite state machine -pattern checker in vhdl

When a certain serial binary communication channel is operating correctly, all blocks of 0's are of even length and all blocks of 1's are of odd length. The machine should produce and output pulse z = 1 whenever discrepancy from the above pattern is detected. Example: X : 0 0 1 0 0 0 1 1 1 0 1 1 0 0… Z : 0 0 0 0 0 0 1 0 0 0 1 0 1 0… library ieee; use ieee.std_logic_1164.all; entity fsm_prob3 is     port (     clk                : in ...

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User defined package in vhdl example

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; package combo_logic is   function mux2x1 (d1,d2,sel : std_logic) return std_logic;   function parity_chk (signal d_in : std_logic_vector) return std_logic;   function left_shift (signal d_in : std_logic_vector; signal shift_by : integer)  return bit_vector;   function right_shift (signal d_in : std_logic_vector; signal shift_by : integer) return bit_vector;    end combo_logic; package body combo_logic is -------------------------------------------------------------------------------- --function...

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4 bit full adder verilog code

module full_adder_4b(sum,cout,a,b,cin);    output [3:0] sum;    output     cout;    input [3:0]     a,b;    input     cin;    full_adder f1 (sum[0], cout0, a[0], b[0], cin);    full_adder f2 (sum[1], cout1, a[1], b[1], cout0);    full_adder f3 (sum[2], cout2, a[2], b[2], cout1);    full_adder f4 (sum[3], cout, a[3], b[3], cout2);    endmodu...

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D latch verilog code

module d_latch(q, q_bar, d_in, enb);    output q,q_bar;    input  d_in;    input  enb;    nand g1 (s, d_in, enb),         g2 (r, d_bar, enb);       not g3 (d_bar,d_in);    nand g4 (q, s, q_bar);    nand g5 (q_bar, r, q);    endmodule   ...

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4:16 decoder verilog code

module decoder_4x16 (d_out, d_in);    output [15:0] d_out;    input [3:0]      d_in;    parameter tmp = 16'b0000_0000_0000_0001;    assign d_out = (d_in == 4'b0000) ? tmp   :                (d_in == 4'b0001) ? tmp<<1:                (d_in == 4'b0010) ? tmp<<2:            (d_in ==...

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Priority encoder verilog code

module prio_enco_8x3(d_out, d_in);    output [2:0] d_out;    input [7:0] d_in ; assign d_out = (d_in[7] ==1'b1 ) ? 3'b111:                (d_in[6] ==1'b1 ) ? 3'b110:                (d_in[5] ==1'b1 ) ? 3'b101:                  (d_in[4] ==1'b1) ? 3'b100:                 ...

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Parity generator structural vhdl code

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity parity_gen is     port (     clk       : in  std_logic;     rst_a     : in  std_logic;     valid_in  : in  std_logic;     d_in      : in  std_logic;          -- input serial data stream     valid_out : out...

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Barrel shifter with multi cycle and textio vhdl code

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity barrel_shifter_multi is     port (     d_in          : in bit_vector (7 downto 0);     clk, rst_a    : in bit;     shift_lt_rt   : in bit;                     --0=>left shift , 1=> right shift    ...

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