Run multiple testcases in System Verilog in Questasim

Let there are two test cases. testcase1 and testcase2 1-First complie them using the command(for questasim)  vlog  top.sv test_case1.sv vlog   top.sv   test_case2.sv 2-To run them use command as given below  vsim top +test_case1 vsim  top  +test_case2...

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System Verilog Inheritance example

/*-----------------------------------BASE CLASS----------------*/ class base;    logic [7:0] data;    task increament(logic[7:0] temp);      data=temp+1;    endtask // increament    task random();       this.data=$random;    endtask // random endclass // base /*-----------------------------------DERIVED CLASS----------------*/ class derived extends base;    logic[7:0] packet[];    int size;    function new(int size);    ...

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Single Port RAM in VHDL using generate statement

//////////////////////////////////////////////////////////////////////////////// Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//contact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// library ieee;use ieee.std_logic_1164.all;entity memory_sp is    port (    clk      : in  std_logic;    address  : in ...

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4x1 mux primitive example in verilog

/////////////////////////////////////////////////////////////////////////////////////////////// // Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//contact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// primitive mux_4x1(muxed_out,sel_1,sel_0,data1,data2,data3,data4);   output muxed_out;   input  sel_1,sel_0;   input  data1,data2,data3,data4;  ...

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D flip flop primitive in verilog example

//////////////////////////////////////////////////////////////////////////////// Design Name : dflip flop primitive// File Name   : d_flipflop.v// Function    : // Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//contact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// primitive d_flipflop(q,clear,clk,d);   output q;   reg q;  ...

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Vending Machine in Verilog

 //////////////////////////////////////////////////////////////////////////////// Design Name : Vending Machine// File Name   : vending.v// Function    : at 15 rupee  req op will come // Author      : Sidharth//Permission   : This code only for educational purpose only//cintact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// module vending(out,coin,clk,rst);     output reg...

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Simple arbiter example in verilog

 //////////////////////////////////////////////////////////////////////////////// Design Name : Design a Priority resolver for four requests using least recently algorithm.// File Name   : priority_resolver_new.v// Function    : priority resolver// Author      : Sidharth(DVLSI 31)//Permission   : This code only for educational purpose only//cintact      :sidharth.sankar77@gmail.com////////////////////////////////////////////////////////////////////////////// module...

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